A78 is basically a mild refinement to A77. X1 is a souped-up A78. * Move from 4 to 5-wide decoder (A14 is 8-wide) * Double number of 128-bit SIMD from 2 to 4

A78 is basically a mild refinement to A77. X1 is a souped-up A78. * Move from 4 to 5-wide decoder (A14 is 8-wide) * Double number of 128-bit SIMD from 2 to 4 (A14 is 4) * Moving multiplication into a second ALU allows simultaneous multiplication and division (on both A78 and X1) * Minimum L1 cache at 64kb instead of 32kb with a 64kb option (A14 is 128 d-cache and 196 i-cache) * L1 bandwidth on A78 and X1 doubled over A77 (probable 2-4x as wide on A14) * Double L2 cache from 512kb to 1mb (A14 has 8mb L2, but no L3) * Double maximum amount of L3 cache from 4mb to 8mb (for a potential 9mb cache vs 8mb for A14) * Still ARMv8.2 (A14 is ARMv8.4 which brings some extra instructions for pointer security, virtualization, JS integer conversion, complex number SIMD, SHA512/SHA-3 hardware, int dot products, and some other stuff -- probably the biggest performance difference here will be the 1-2% for JS conversion) * Increase BTB from 64 to 96 entries (Not sure about A14, but probably more) * Increase TLB from 1k to 2k pages (A14 is 3072 pages) * mops bandwidth goes from 6 to 8 mops (not sure about A14, but 8+ for sure) * uop cache goes from 1.5k entries to 3k entries (I seem to remember hearing 2k entries for the A12, but I don't know) * mops dispatch also goes from 6 to 8 (once again , not sure about A14, but 8+ for sure) * uops dispatch increases from 10 in A77 to 12 in A78 to 16 in X1 (I'd guess Apple's at least this wide) * reorder buffer increasing from 160 to 224 entries (A14 ROB is somewhere around 630 entries) ARM's claims that with all three processors at 3GHz, the A78 is 7% faster than A77 and the X1 is 20-30% faster depending on the workload. I'd guess that SIMD float-heavy performance between X1 and A14 is very close. More interesting is the x86 comparison (let's look at zen 2). X1 has twice the L1 cache (64 vs 32k), but considering AMD lowered this amount, I doubt it's a real advantage more than different ISA and microarchitectures. Likewise X1 with 1mb of L2 vs 512kb for zen 2 probably doesn't matter too much (AMD redid the cache in zen 3 and stuck with 512kb while Intel still uses 256k). Zen 2 has 16 L0 BTB vs 96 L0 BTB for X1, but this might be microarchitecture more than anything as well as X1 drops to 2k L2 entries vs 7k for Zen 2. I don't know if 8mb L3 is shared in X1, but I'd assume so in which case 16mb for zen 2 is a definite advantage. The decode width is now 20% wider than zen, but x86 instructions are around 15% more dense, so I'd guess it's about the same. X1 has 3k uop cache entries vs 4k on x86, but I suspect x86 needs more to avoid hitting those complex decoders at all costs. AMD dispatches 6 int uops and 4 float uops per cycle while X1 does 16 uops per cycle. I don't know about ARM, but AMD's perceptron predictor is probably better (it seems like Apple or ARM would make a big deal about this if they'd made the investment -- Samsung did). Given AMD has 19 stages instead of 13 in the X1, a better predictor is needed to offset penalties. X1 and Zen 2 both have identical 224-entry reorder buffer. X1 has 2 AGU, 1 AGU/load and 2 load/store while zen 2 has 3 AGU, 2 load/store, and 1 store. Zen 2 and X1 AGU are both 256-bit wide. I can't find store queue length for X1, but bigger queues could be an advantage to AMD (I suspect so as ARM probably wouldn't want the extra power draw). A76 seems to have similar instruction cycle counts to Zen 2 and I assume they haven't gotten worse since. X1 has four 128-bit SIMD while Zen 2 has two 256-bit SIMD. If you can use wider SIMD, AMD has an advantage, but if there's lots of smaller SIMD, then X1 should have an advantage). Zen 2 has 4 integer ALU with one capable of multiplication, another capable of division, and another with a CRC (cyclic redundancy checking). X1 is identical (except I don't know if it has a CRC). X1 very likely comes close to Zen2 and even A14 in integer performance while being a bit more bottlenecked in float performance. With not one, but two ARM designs now taking on x86 so handily, perhaps it's about time we start considering that ISA maybe does matter more than Intel has claimed over the years.