4 ms·

Another example - M1s can't do SMT, no one is denying that they are good chips but there's a lot of catching up for them to do. > And all of the M1 Macs have b

Another example - M1s can't do SMT, no one is denying that they are good chips but there's a lot of catching up for them to do. > And all of the M1 Macs have blazingly fast memory access. Remember, it's an SoC—the memory is on the same die as the CPUs, GPUs and they all have equal access to it. No bus to go across. What does this even mean? Memory works at a certain voltage, clock speed, and has a capped rate at which it can transfer data if those are kept constant. For DDR4-3200 it's generally 3,200 MTs (megatransfers/sec). What does every core has equal access to it mean? What does soldering SDRAM change in terms how many transfers/sec it can do? What do you mean there is no bus? > The M1 already has features no "desktop" chip has, such as 8 instruction decoders. What makes going wide a "desktop" class feature? Going wide isn't free, there is transistor cost associated. A M1 chip has 16 billion transistors for 8 cores. AMD's EPYC Rome has 39.54 billion transistors for 64 cores. That's 8 times as many cores. And that's including ~9 billion transistors just for the I/O die. If you look at just the chiplets, AMD's 8 Core complexes take up only 3.9 billion transistors each. And these are 8 high performance cores with SMT, even removing GPU/NPU engines from M1, AMDs design clearly has a lower transistor cost. > The Zen3 barely beats the M1 AMD was't trying to make an entry level laptop chip, so it's not good at being a entry level laptop chip? How do you think M1 would fare if we try to compare them on datacenter CPU metrics? I understand why everyone is excited, but they aren't looking at the whole picture.

alwillis 6y ago
Just read "Why Is Apple’s M1 Chip So Fast?" [1] to answer most of these questions. I’ll just hit the obviously erroneous issues here. A M1 chip has 16 billion transistors for 8 cores. AMD's EPYC Rome has 39.54 billion transistors for 64 cores. It doesn't make sense to compare the M1 with the EPYC Rome. They couldn't more different and were developed for dramatically different use cases. (I also don't think it's not a good look when folks feel compelled to state Apple's M1 isn't as fast as AMD's $4000 64-core processor, as if this means anything. Of course the EPYC Rome is faster--duh. Anyways…) 16 billion transistors on the M1 SoC (emphasis on system) gets you an 8-core GPU, a 16-core Neural Processor, a Digital Signal Processor, a Secure Enclave, image processing unit, video encoder/decoder and of course 8 CPU cores and 8 or 16 Gb of memory. Instruction decoders deal with the out of order execution of the instructions; more decoders enables you to have more instructions "in flight" as they say for the execution cores to run in parallel. Again, you should read the article for the details, but due to the legacy architecture and technical debt of a 40 year-old instruction set, not to mention with instructions ranging in size from 1 to 15 bytes, it's not easy for the decoders to juggle all of the instructions to do out of order execution of instructions. Yes, even the EPYC Rome only has 4 instruction decoders. Meanwhile, the instructions for Apple's Firestorm cores are all the same size, making decoding the instructions much easier and faster; so much so that the M1 has 8 decoders, which is unheard of in a mainstream processor. Here's the bottom line quote from the article: "In fact, adding more causes so many other problems that four decoders according to AMD itself is basically an upper limit for how far they can go. This is what allows the M1 Firestorm cores to essentially process twice as many instructions as AMD and Intel CPUs at the same clock frequency." Apple and AMD solved the "get as many instructions in the pipeline as possible and process them as quickly as possible" problem two different ways. AMD does it with threading and many cores; Apple does it by increasing the number of instruction decoders and by having 60+ Gb/s bandwidth with a 128-bit bus. Apple didn't implement SMT because they don't need it; they have no issues with keeping their instruction pipeline full. Bottom line: Apple's approach has more headroom than AMD's approach. They can't add more instruction decoders, so they crank up the clock speed and the threads to execute more instructions per clock cycle. But the M1 is so efficient, it processes twice as many instructions at the same clock frequency. The M1 runs at 3.2 GHz; it's got a higher ceiling because Apple can add more cores and increase the clock speed a lot before it gets anywhere near the power consumption and other physical limits that AMD is starting to run up against. [1]: https://debugger.medium.com/why-is-apples-m1-chip-so-fast-3262b158cba2 https://debugger.medium.com/why-is-apples-m1-chip-so-fast-32...
- dhruvdh 6y ago
  > It doesn't make sense to compare the M1 with the EPYC Rome. They couldn't more different and were developed for dramatically different use cases. The author of your beloved article compared M1 to Zen 3, and all Zen 3 CPUs use the same 8-core chiplet. From the cheapest 6-core Ryzen 3 5600 to the 64 core EPYC. All of them are made of the the exact same chiplets, just then number of chiplets varies. If you have 2 chiplet you get 16 cores, etc. > Yes, even the EPYC Rome only has 4 instruction decoders. It doesn't have "4 decoders"; it's just one 4-way instruction decoder. It's not the same thing. > Firestorm cores to essentially process twice as many instructions as AMD and Intel CPUs at the same clock frequency. A decoder doesn't not process instructions, it only interprets them and splits it up into smaller instructions. It doesn't make sense to compare number of instructions across different ISAs anyway, ARM has smaller, simpler, and on account of that more numerous instructions. One x86-64 instruction more often than not maps to multiple ARM instructions. It just makes no sense to compare counts. I sort of stopped reading your comment around here, sorry about that.

alwillis 6y ago

Just read "Why Is Apple’s M1 Chip So Fast?" [1] to answer most of these questions. I’ll just hit the obviously erroneous issues here. A M1 chip has 16 billion transistors for 8 cores. AMD's EPYC Rome has 39.54 billion transistors for 64 cores. It doesn't make sense to compare the M1 with the EPYC Rome. They couldn't more different and were developed for dramatically different use cases. (I also don't think it's not a good look when folks feel compelled to state Apple's M1 isn't as fast as AMD's $4000 64-core processor, as if this means anything. Of course the EPYC Rome is faster--duh. Anyways…) 16 billion transistors on the M1 SoC (emphasis on system) gets you an 8-core GPU, a 16-core Neural Processor, a Digital Signal Processor, a Secure Enclave, image processing unit, video encoder/decoder and of course 8 CPU cores and 8 or 16 Gb of memory. Instruction decoders deal with the out of order execution of the instructions; more decoders enables you to have more instructions "in flight" as they say for the execution cores to run in parallel. Again, you should read the article for the details, but due to the legacy architecture and technical debt of a 40 year-old instruction set, not to mention with instructions ranging in size from 1 to 15 bytes, it's not easy for the decoders to juggle all of the instructions to do out of order execution of instructions. Yes, even the EPYC Rome only has 4 instruction decoders. Meanwhile, the instructions for Apple's Firestorm cores are all the same size, making decoding the instructions much easier and faster; so much so that the M1 has 8 decoders, which is unheard of in a mainstream processor. Here's the bottom line quote from the article: "In fact, adding more causes so many other problems that four decoders according to AMD itself is basically an upper limit for how far they can go. This is what allows the M1 Firestorm cores to essentially process twice as many instructions as AMD and Intel CPUs at the same clock frequency." Apple and AMD solved the "get as many instructions in the pipeline as possible and process them as quickly as possible" problem two different ways. AMD does it with threading and many cores; Apple does it by increasing the number of instruction decoders and by having 60+ Gb/s bandwidth with a 128-bit bus. Apple didn't implement SMT because they don't need it; they have no issues with keeping their instruction pipeline full. Bottom line: Apple's approach has more headroom than AMD's approach. They can't add more instruction decoders, so they crank up the clock speed and the threads to execute more instructions per clock cycle. But the M1 is so efficient, it processes twice as many instructions at the same clock frequency. The M1 runs at 3.2 GHz; it's got a higher ceiling because Apple can add more cores and increase the clock speed a lot before it gets anywhere near the power consumption and other physical limits that AMD is starting to run up against. [1]: https://debugger.medium.com/why-is-apples-m1-chip-so-fast-3262b158cba2 https://debugger.medium.com/why-is-apples-m1-chip-so-fast-32...

dhruvdh 6y ago
> It doesn't make sense to compare the M1 with the EPYC Rome. They couldn't more different and were developed for dramatically different use cases. The author of your beloved article compared M1 to Zen 3, and all Zen 3 CPUs use the same 8-core chiplet. From the cheapest 6-core Ryzen 3 5600 to the 64 core EPYC. All of them are made of the the exact same chiplets, just then number of chiplets varies. If you have 2 chiplet you get 16 cores, etc. > Yes, even the EPYC Rome only has 4 instruction decoders. It doesn't have "4 decoders"; it's just one 4-way instruction decoder. It's not the same thing. > Firestorm cores to essentially process twice as many instructions as AMD and Intel CPUs at the same clock frequency. A decoder doesn't not process instructions, it only interprets them and splits it up into smaller instructions. It doesn't make sense to compare number of instructions across different ISAs anyway, ARM has smaller, simpler, and on account of that more numerous instructions. One x86-64 instruction more often than not maps to multiple ARM instructions. It just makes no sense to compare counts. I sort of stopped reading your comment around here, sorry about that.