3 ms·

At scale, cores are only a small part of the equation. https://images.anandtech.com/doci/13124/IF%20Power%20EPYC.png https://images.anandtech.com/doci/13124/IF

by hajile 6y ago

At scale, cores are only a small part of the equation. https://images.anandtech.com/doci/13124/IF%20Power%20EPYC.png https://images.anandtech.com/doci/13124/IF%20Power%20EPYC.pn... Given that scaling, you're looking at 140w between 64 cores which is right at 2w per core. The all-core turbo for TR is 3GHz. If we assume linear scaling on M1 cores, if you dropped them in to replace the x86 cores and the had to reduce from 3.2GHz at 4w down to 2w per core, the all-core turbo would be a mere 1.6GHz AND about a third less cache per core. TSMC claims 30% less power going from 7nm to 5nm. That means those x86 cores power usage drops from 2w to 1.4w. With the same linear scaling and 4w at 3.2GHz, the M1 design is now operating at 1.1GHz competing with a part that is still 3GHz and the M1 still has only 3mb of cache per core instead of 4.5mb. Now, I'm betting that actual power usage is 3w which bumps frequency up to 1.5GHz. Still half the frequency, but possibly close enough in performance to Zen 3 at that frequency. EDIT: It's apparently 3.45w during cinebench according to these benchmarks. https://twitter.com/panzer/status/1328715510100344833 https://twitter.com/panzer/status/1328715510100344833 I'm betting that if they didn't bottleneck on the IO that the M1 would perhaps be faster, but at that scale, interconnects are a much, much larger issue than the cores themselves.

hajile 6y ago
Adding on to that Zen 3 chiplet is 4.15B transistors. The consumer IO die is 2.09B transistors. The Threadripper IO dies is 8.34B transistors. M1 is 16B transistors. A14 is 11.6B transistors. That difference is mostly 2 firestorm cores/cache, 4 GPU cores, another DDR4 controller, and some Thunderbolt/PCIe. Taking a ruler to a die shot and multiplying that area by transistor density (16B/119mm^2) gives us somewhere around 500M transistors per core plus 3mb of cache. Adjusting out to 4.5MB per core to match Zen 3 adds another 75-100M transistors. Zen 3 gives 518M transistors per core, but that includes interconnects. Taking a ruler to the core reveals about 14% of the die is interconnect, SMU, and wafer tests (about 580M transistors). Subtracting that from 4.15B and dividing into even core/cache gives 446M transistors per core. We'll assume an identical IO cost of 8.5B transistors and 150M transistors of interconnect per core. (64 * (600 + 150)) + 8500 is 56.5B transistors and 420mm^2 total area. A zen 3 chip with similar densities would be 310mm^2. No matter how you slice and dice that, Apple's chip is going to be significantly more expensive than AMD's chip. Thinking anything different is a pipe dream. EDIT: also note that formal verification adds a lot to chip pricing.

by hajile 6y ago

hajile 6y ago

Adding on to that Zen 3 chiplet is 4.15B transistors. The consumer IO die is 2.09B transistors. The Threadripper IO dies is 8.34B transistors. M1 is 16B transistors. A14 is 11.6B transistors. That difference is mostly 2 firestorm cores/cache, 4 GPU cores, another DDR4 controller, and some Thunderbolt/PCIe. Taking a ruler to a die shot and multiplying that area by transistor density (16B/119mm^2) gives us somewhere around 500M transistors per core plus 3mb of cache. Adjusting out to 4.5MB per core to match Zen 3 adds another 75-100M transistors. Zen 3 gives 518M transistors per core, but that includes interconnects. Taking a ruler to the core reveals about 14% of the die is interconnect, SMU, and wafer tests (about 580M transistors). Subtracting that from 4.15B and dividing into even core/cache gives 446M transistors per core. We'll assume an identical IO cost of 8.5B transistors and 150M transistors of interconnect per core. (64 * (600 + 150)) + 8500 is 56.5B transistors and 420mm^2 total area. A zen 3 chip with similar densities would be 310mm^2. No matter how you slice and dice that, Apple's chip is going to be significantly more expensive than AMD's chip. Thinking anything different is a pipe dream. EDIT: also note that formal verification adds a lot to chip pricing.