3 ms·
I have checked again. To get analog io, projects can connect to the analog_io pins in the wrapper [1] which connect to the pad through a 150 ohm resistor, and
by rrss 6y ago
I have checked again.
To get analog io, projects can connect to the analog_io pins in the wrapper [1] which connect to the pad through a 150 ohm resistor, and disable the digital GPIO drivers. If that resistor is a problem, user projects can route directly to the pad_no_esd pin.
There are a number of people working on analog or mixed-signal designs inside the caravel harness with analog io.
From caravel/verilog/rtl/README:
> mprj_io: 32 bits general purpose programmable digital or analog I/O
> The user will also have access to the ESD-protected pad connections for analog signals
[1] https://github.com/efabless/caravel/blob/c4c79cdf63d6a7ed7ceec4e0afbabe21fa5f9bfb/verilog/rtl/mprj_io.v#L41 https://github.com/efabless/caravel/blob/c4c79cdf63d6a7ed7ce...
- octoberfranklin 6y agoThose pins are not connected to the external package. See page 4 of the Caravel datasheet here: https://github.com/efabless/caravel/blob/master/doc/caravel_datasheet.pdf Only the digital I/Os are accessible from outside the package. Every entry in the table has either "power", "ground", or "digital {in,out,I/O}" for the "type" column. They appear to have some kind of simple output-only analog driver (see "analog output" in the Summary Description column) but no analog input according to the datasheet.