3 ms·

Just a few low-activity OS & mostly sleeping application threads will barely fill one or two of these typical 'slow' cores you see in big.LITTLE SoC's, so what'

Just a few low-activity OS & mostly sleeping application threads will barely fill one or two of these typical 'slow' cores you see in big.LITTLE SoC's, so what's the point of adding more of them? I don't think lack of general-purpose cores has been a problem for mobile for a long time. I see much more value in heterogeneous SoC's that integrate multiple application-specific blocks that can only do a few things but do them very, very efficiently. This is pretty much what the industry has been moving towards for the past few years anyway, the Apple M1 being a good example of that.

hajile 6y ago
Those "slow" cores are very big and complex in comparison to an actually small core. A53 in 20nm Exynos 5443 is 1mm^2 without cache (0.55mm^2 for 256k cache) and that's the smallest variant I could find numbers for without die shrinks. M0+ is 0.009mm^2 at 40nm. You can probably add another zero with two full node shrinks. M4 is just 0.04mm^2 at 40nm. M7 is probably 2-3x the size and M55 with SIMD (zero architecture relation to A55), but without tensor cores is probably 2-3x that size. Accounting for die shrink and core growth, we basically get back where we started with M55 being around 0.04mm^2 and A53 being around 1mm^2 at 20nm. Even if I were off a further order of magnitude (not likely given that it's still just a 4-stage, in-order core), it would still be only 2/5 the size. I'd note that A55 is bigger than A53 by some amount (I don't think ARM has released that data). If I'm right, you can fit 25 M55 cores in the space of one A53. Even if I'm very off, you could still fit 2.5x as many cores. Dedicated cores for system processes has a few desirable effects. They are on simpler designs less likely to be exploitable with the latest order and timing attacks. They don't need to be interrupted often. This decreases context switching latency (which can exceed actual processing time). Less data moves around the chip decreasing power consumption. Prefetching can be more accurate with a smaller transistor budget and even cache sizes can decreases per core due to single purpose use. Since it's single use, you can also clock gate it completely when not in use. I'd rather like to see a phone chip design with a hundred tiny cores each anchored to one process in place of 4 A55 cores.

hajile 6y ago

Those "slow" cores are very big and complex in comparison to an actually small core. A53 in 20nm Exynos 5443 is 1mm^2 without cache (0.55mm^2 for 256k cache) and that's the smallest variant I could find numbers for without die shrinks. M0+ is 0.009mm^2 at 40nm. You can probably add another zero with two full node shrinks. M4 is just 0.04mm^2 at 40nm. M7 is probably 2-3x the size and M55 with SIMD (zero architecture relation to A55), but without tensor cores is probably 2-3x that size. Accounting for die shrink and core growth, we basically get back where we started with M55 being around 0.04mm^2 and A53 being around 1mm^2 at 20nm. Even if I were off a further order of magnitude (not likely given that it's still just a 4-stage, in-order core), it would still be only 2/5 the size. I'd note that A55 is bigger than A53 by some amount (I don't think ARM has released that data). If I'm right, you can fit 25 M55 cores in the space of one A53. Even if I'm very off, you could still fit 2.5x as many cores. Dedicated cores for system processes has a few desirable effects. They are on simpler designs less likely to be exploitable with the latest order and timing attacks. They don't need to be interrupted often. This decreases context switching latency (which can exceed actual processing time). Less data moves around the chip decreasing power consumption. Prefetching can be more accurate with a smaller transistor budget and even cache sizes can decreases per core due to single purpose use. Since it's single use, you can also clock gate it completely when not in use. I'd rather like to see a phone chip design with a hundred tiny cores each anchored to one process in place of 4 A55 cores.