4 ms·
Not that this will ever matter for someone who isn't a circuit designer, but the "optimal" solution for the latch is actually really bad. If you use a "select"
by kayson 6y ago
Not that this will ever matter for someone who isn't a circuit designer, but the "optimal" solution for the latch is actually really bad.
If you use a "select" block (which should really be called "mux") and tie the output to the input, you create a race condition. If the data input is 1, and you change set from 1 to 0, the output can actually glitch to 0 for a very short period of time, which is a big no-no. (If you draw the equivalent circuit out with just nand gates and assume they all have some delay between input and output, you'll see why).
A safer solution would be to cross couple two nand gates into an SR latch [0], use another two nand gates to control the Set and Reset signals, and an inverter to create NOT(data).
Of course in reality, a latch is usually custom built out of transistors rather than logic gates, but there are some cases where I've used logic-gate-latches to make things easier.
</pedanticism>
[0] http://electronics-course.com/sr-nand-latch http://electronics-course.com/sr-nand-latch
- sitzkrieg 6y agoin the yearly reposting of this on hn i always am annoyed to remember some of the best-on-paper isms of the book
- jsmith45 6y agoSince the latch is only used as a component of the flip-flip and edge sensitive logic does not care about glitches except on the clock line or any asynchronous set/resets (which are not used in this design) I find that rather unimportant. Especially because the d-flipflops found in standard cell libraries are frequently implemented as what amounts to two muxes and some inverters. For a design that uses latches as stand-alone components the glitch considerations become a lot more important.
- kayson 6y agoIn practical designs, flip flop outputs are regularly used as clock inputs and asynchronous set/reset inputs. If you used this latch as the output latch in a flip flop, it would glitch on the falling edge of the flip flop clock. I didn't go through the entire game, so its entirely possible that it would not affect this particular "design". But as its far more educational than practical, I think its still worth mentioning. > Especially because the d-flipflops found in standard cell libraries are frequently implemented as what amounts to two muxes and some inverters. I'm curious where you've seen that implementation because I've never seen anything like that. Most of what I've seen uses two tri-state inverter latches.
- userbinator 6y agoNot the one you're replying to, but look up "transmission gate latch". As for an actual processor that uses them, see the RCA CDP1802, for which a die photo and reverse engineered gate-level schematic are available.
- kayson 6y agoAh. Duh. I was thinking static cmos logic/nand gate mux in my head, probably because that's how you build it in the game. Definitely have seen tgate flip flops. They seem to be less in fashion now though I'm not exactly sure why.