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A better measurement would be million transistors per square milimeter(Mtr/mm2). So Intel's self reported 44Mtr/mm2 @ 14nm, and 100Mtr/mm2 @ 10nm(but currently
by petra 6y ago
A better measurement would be million transistors per square milimeter(Mtr/mm2).
So Intel's self reported 44Mtr/mm2 @ 14nm, and 100Mtr/mm2 @ 10nm(but currently 10nm is having problems).
Comparing this to Tsmc's 170Mtr/mm2 @ 7nm and 250Mtr/mm2 @ 5nm - is a pretty valid comparison, I think.
- bigbubba 6y agoSo if anything, a naive 'nm' comparison is actually too favorable to Intel? That's amusing, since I've heard it suggested by Intel fanboys that it was the other way around.
- deleted 6y ago[deleted]
- ksec 6y agoBecause your parent got it mixed up. 170 Mtr/mm2 refers to 5nm. TSMC's 7nm is roughly 100 Mtr/mm2 depending which 7nm you are referring to as TSMC has quite a few variants. So yes, Intel's 10nm is roughly speaking the same as TSMC's 7nm. Just to give another perspective, by the end of 2020, TSMC would have shipped more 5nm wafers then Intel's 10nm has ever shipped.
- ConcernedCoder 6y ago3D transistors so cubic milimeter might be better?
- wtallis 6y agoThe transistors are 3D only in the sense that FinFETs aren't just wires on top of a flat surface of doped silicon. There's still no 3D stacking of one transistor on top of another, and transistor density is still best measured by how much 2D wafer area is occupied by a transistor. This is very different from the situation for NAND flash memory, where the memory cell array is genuinely 3D and pushing toward hundreds of layers of memory cells, so volumetric measurements are starting to become useful. (However, the horizontal dimensions of various 3D NAND designs are roughly similar, so comparing simply in terms of layer count is a good first approximation of bit density.)
- Sohcahtoa82 6y agoWhy aren't we stacking layers of transistors in CPUs? Is it because of heat dissipation issues?
- fpoling 6y agoYes, but another reason is that in flash only tiny amount of cells are active at time. So even with much bigger cells that are required for reliable 3D stacking and more heat production per cell it is still very ok.
- themule 6y agowe are starting to and beginning to stack transistors on top of each other. It is a heat dissipation issue but it seems like we will be done.
- xiphias2 6y agoWhat really matters is energy efficiency (watts/transistor or watts/some computation that utilizes the chip well)
- The_rationalist 6y agoInteresting but what is the Mtr/mm2 for a "true" 3nm transistor? How big is the gap with the marketing names?
- mlindner 6y agoYou can run the math yourself, but its 111,111 Mtr/mm2.
- The_rationalist 6y agoThat's doesn't make sense: TSMC 5nm has 170 Mtr/mm2 so TSMC 5nm is smaller than true 3nm? No way.
- solarmist 6y ago111,111 MTr/mm2 >> 170 MTr/mm2
- The_rationalist 6y agoMy bad, as a non native English reader I read 111.111 Okay so the gap is a x100 :0
- mlindner 6y agoThe reality is that not all transistors are the same size. They vary in size depending it's exact purpose and how many other transistors it's driving. To the point where they can be up to macro size visible with the human eye in audio switching equipment for example.