3 ms·

No, Apple doesn't run the translated code with a weak memory model, Rosetta 2 toggles the total store ordering (which the M1 supports) on when running its code.

No, Apple doesn't run the translated code with a weak memory model, Rosetta 2 toggles the total store ordering (which the M1 supports) on when running its code. Microsoft's translator (and QEMU?) does insert extra barriers to make it run on a weak memory model, because they are designed to run on HW without TSO.

CalChris 6y ago
Yes, Apple added a CPU mode bit. From the article: Note: writing an x86 emulator on ARM forces you to deal with this in a particularly messy way because you never know when reordering will be a problem so you typically have to insert a lot of memory barriers. Or you can follow Apple’s strategy and add a CPU mode that enforces x86/x64 memory ordering, turning that on when emulating. I'm a little surprised+happy the ARM architectural license allowed this.
- floatboth 6y ago
  Why wouldn't it? A stronger memory model doesn't break anything in the ISA. You can always go stronger, it's not a problem even for native applications, it would just make them slightly slower. What is surprising with Apple is that they were allowed to add extra instructions for machine learning related math (yeah, CPU instructions in addition to a dedicated separate "neural engine" on the chip: https://news.ycombinator.com/item?id=24471699 https://news.ycombinator.com/item?id=24471699)
  - CalChris 6y ago
    After doing a little web research, I'll conclude that it's impossible to know from the outside what the restrictions are on ARM architectural licensees other than they have to pass the ARM compatibility test suite. New instructions (probably not), new modes (looks like), dunno (definitely). However, Apple is one of the founding ARM partners and it is rumored they have a special license (not all licenses are created equal). Clearly they are doing this mode thing. Whether Samsung could get away with the exact same thing is a good question. I'm going to guess that NVidia can.
miohtama 6y ago
How does the toggle work? Is it per thread, CPU affinity, per process, CPU flag or something totally different?
- abbeyj 6y ago
  It seems to be a CPU flag. This is managed by the kernel so that it is on for Rosetta 2 processes and off for everything else. See https://github.com/saagarjha/TSOEnabler https://github.com/saagarjha/TSOEnabler

CalChris 6y ago

Yes, Apple added a CPU mode bit. From the article: Note: writing an x86 emulator on ARM forces you to deal with this in a particularly messy way because you never know when reordering will be a problem so you typically have to insert a lot of memory barriers. Or you can follow Apple’s strategy and add a CPU mode that enforces x86/x64 memory ordering, turning that on when emulating. I'm a little surprised+happy the ARM architectural license allowed this.

floatboth 6y ago
Why wouldn't it? A stronger memory model doesn't break anything in the ISA. You can always go stronger, it's not a problem even for native applications, it would just make them slightly slower. What is surprising with Apple is that they were allowed to add extra instructions for machine learning related math (yeah, CPU instructions in addition to a dedicated separate "neural engine" on the chip: https://news.ycombinator.com/item?id=24471699 https://news.ycombinator.com/item?id=24471699)
- CalChris 6y ago
  After doing a little web research, I'll conclude that it's impossible to know from the outside what the restrictions are on ARM architectural licensees other than they have to pass the ARM compatibility test suite. New instructions (probably not), new modes (looks like), dunno (definitely). However, Apple is one of the founding ARM partners and it is rumored they have a special license (not all licenses are created equal). Clearly they are doing this mode thing. Whether Samsung could get away with the exact same thing is a good question. I'm going to guess that NVidia can.

miohtama 6y ago

How does the toggle work? Is it per thread, CPU affinity, per process, CPU flag or something totally different?

abbeyj 6y ago
It seems to be a CPU flag. This is managed by the kernel so that it is on for Rosetta 2 processes and off for everything else. See https://github.com/saagarjha/TSOEnabler https://github.com/saagarjha/TSOEnabler