4 ms·

A weak memory model. See https://riscv.org/wp-content/uploads/2018/05/14.25-15.00-RISCVMemoryModelTutorial.pdf https://riscv.org/wp-content/uploads/2018/05/14.2

by my123 6y ago

A weak memory model. See https://riscv.org/wp-content/uploads/2018/05/14.25-15.00-RISCVMemoryModelTutorial.pdf https://riscv.org/wp-content/uploads/2018/05/14.25-15.00-RIS... (by Dan Lustig at Nvidia, NV is both very involved in Arm and RISC-V).

zozbot234 6y ago
It has a weak memory model by default, but you can opt in to TSO (like x86) as an optional extension.
- my123 6y ago
  And for Arm too, you can ship stronger memory models up to SC. There's also the RCpc extension for memory accesses w/ another memory model there.
  - jabl 6y ago
    Is RCpc still multi-copy atomic? (Which AFAIK is a guaranteed behavior of the Aarch64 memory model)
    - my123 6y ago
      No difference on that front, yep.