Clock frequency is not everything and it's not necessarily good if somebody tries to solve something with raw power. Unfortunately the RISC-V instruction set is

Clock frequency is not everything and it's not necessarily good if somebody tries to solve something with raw power. Unfortunately the RISC-V instruction set is crippled performance-wise, by design. It looks like a clone of MIPS, which is a textbook implementation of a clean and well-thought ISA, except that the delay slot and a couple of things have been removed. Critical and frequent code fragments are two times longer compared to ARM, needing 2x the CPU clocks to execute, so there goes the high clock frequency... For details, take a look at this: https://news.ycombinator.com/item?id=24958423 https://news.ycombinator.com/item?id=24958423