4 ms·

> It may just be the fact that it is on a cutting edge 5nm process with a SoC design. Yup. It's fast because it's got short distances to memory and everythin

> It may just be the fact that it is on a cutting edge 5nm process with a SoC design. Yup. It's fast because it's got short distances to memory and everything else. Shorten the wire to memory cells and not only can you make signaling faster and run the memory at faster clock speed but you can do it with less accessory hardware for signal conditioning and error correction, which saves complexity and power. Using shorter paths to memory also lets you use lower voltages, which means less waste heat and less need to spend effort on cooling and overall power savings for the chip. Shortening the wire also lowers latency between all the various on board devices, so communicating everywhere is faster. There's a reason that manufacturers used to be able to "speed" up a chip by just doing a die shrink - photographically reducing chip masks to make them smaller, which also made them faster with relatively small amounts of work. As the late Adm. Grace Hopper put it, there are ever so many picoseconds between the two ends of a wire.

baybal2 6y ago
> Shortening the wire also lowers latency between all the various on board devices, so communicating everywhere is faster. A maximum of a few nanoseconds. Not much in comparison to an overall memory system latency. > Shorten the wire to memory cells and not only can you make signaling faster and run the memory at faster clock speed but you can do it with less accessory hardware for signal conditioning and error correction, which saves complexity and power. You cannot run away from that with just shorter PCB distance. The circuitry for link training is mandated by the standard. You will need a redesigned memory standard for that.
Taniwha 6y ago
Until the late 90s on-chip wire delays were something we just didn't care much about speed was limited by gate capacitance - we got speedups when we shrunk the gate sizes on transistors - after the mid 90s RC delays in wires started to matter (not speed of light delays, how fast you can shuffle electrons in there to fill up the C) soon after it got worse because wire RC delays don't scale perfectly with shrinks because of edge effects - this was addressed in a number of ways, high speed systems reduced the R by switching from Al wires to Cu, tools got better able to model those delays and synthesize and do layout at (almost) the same time

baybal2 6y ago

> Shortening the wire also lowers latency between all the various on board devices, so communicating everywhere is faster. A maximum of a few nanoseconds. Not much in comparison to an overall memory system latency. > Shorten the wire to memory cells and not only can you make signaling faster and run the memory at faster clock speed but you can do it with less accessory hardware for signal conditioning and error correction, which saves complexity and power. You cannot run away from that with just shorter PCB distance. The circuitry for link training is mandated by the standard. You will need a redesigned memory standard for that.

Taniwha 6y ago

Until the late 90s on-chip wire delays were something we just didn't care much about speed was limited by gate capacitance - we got speedups when we shrunk the gate sizes on transistors - after the mid 90s RC delays in wires started to matter (not speed of light delays, how fast you can shuffle electrons in there to fill up the C) soon after it got worse because wire RC delays don't scale perfectly with shrinks because of edge effects - this was addressed in a number of ways, high speed systems reduced the R by switching from Al wires to Cu, tools got better able to model those delays and synthesize and do layout at (almost) the same time