3 ms·
This is exactly how the hardware works and what micro-ops are, on any system with a u-op cache or trace cache those decoded instructions are cached and used ins
by djcapelis 6y ago
This is exactly how the hardware works and what micro-ops are, on any system with a u-op cache or trace cache those decoded instructions are cached and used instead of decoding again. Unfortunately you still have to decode the instructions at least once first and that bottleneck is the one being discussed here. This is all transparent to the OS and not visible outside a low level instruction cache though, which means you don’t need a major OS change, but arguably if you were willing to take that hit you could go further here.
- FeepingCreature 6y agoSo what stops x86 from adding the micro-ops as a dedicated alternate instruction set, Thumb style? Maybe with the implication that Intel will not hold the instruction set stable between chips, pushing vendors to compile to it on the fly?
- freemint 6y agoMirco Ops are usually much wider than instructions of the ISA. They are usually not multiple of 8 bits wide either. An dedicated alternative instruction set would be possible but that would take die space and make x86_64+mine even harder to decode.