They share the underlying storage (i.e. they are aliased) but they are independently addressed, and thus they consume instruction encoding space. Not saying th

They share the underlying storage (i.e. they are aliased) but they are independently addressed, and thus they consume instruction encoding space. Not saying that it's not interesting to know how much actual storage the register file offers; just highlighting that TFA focuses on the instruction encoding angle of the question, which is also important. CPU architectures are masterpieces of tradeoffs. Put too many registers and your instructions steam is not dense enough and you cannot keep your cpu busy due to stalls in the fetch phase. Also context switches become expensive (there are solutions to that though). Put to few registers and you have to spill registers to memory too often, and thus also consume precious instruction stream space.