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Gotta say I'm not a fan of this article. A few points I really disagree with: 1) It puts way too much emphasis on the ISA being a driver for performance. Peopl

Gotta say I'm not a fan of this article. A few points I really disagree with: 1) It puts way too much emphasis on the ISA being a driver for performance. People have been making this claim against x86 forever, going back to the 90s when RISC chips started putting up some very impressive performance numbers. Lots of talk about how the x86 ISA was out of runway. This period existed fo a grand total of about 4 years (94 thru 97) until the Pentium II hit the market, which allowed PCs to start cutting into the workstation market. AMD creating the x86-64 extension handled the addressing limitation well too, letting it flourish in the server space as well. 2) The author seems to think Intel or AMD cannot make SoCs because of their business model. This really isn't the case, and both companies have slowly been moving more "stuff" on package. AMD is already there with the xbox an playstation chips they manufacture. AMD's chiplet approach would be particularly adroit at exploiting this. I get the feeling both AMD and Intel would LOVE it if PC vendors started demanding SoCs. And while the M1 has lots of little speciality processors onboard, both AMD and Intel have more robust processor I/O. That's by design: The M1 isn't designed for the person who needs a gazillion PCI-E lanes for storage and networking (the M1 is likely has half the PCI-E lanes as consumer Zen2/3 cpus and 1/4th to 1/8th compared to Threadripper and EPYC) 3) Glosses over the fact that one of the greatest challenges in computer architecture is coping with the so-called "memory wall": there's a growing latency chasm between cache and memory. Apple cleverly mitigates this by using very fast, low latency memory (LPDDR4x 4266 MT/s vs DDR4 at 3200 MT/s in x86 CPUs). But beyond how many MT/s you're operating with, I would love to see some latency figures. They likely blow your typical consumer DIMMs out of the water. Both AMD and Intel wok around this limitation with larger caches and smarter prefetching, but that only gets you so far. edit: And I would wager much of its impressive performance figures comes from Apple's approach to addressing the memory wall. Memory latency benchmarks seem to strongly favor the M1 over both AMD and Intel CPUs.

pclmulqdq 6y ago
The Intel ISA has some very powerful instructions that allow it to keep performance up, but unfortunately decoding n x86 instructions involves doing a number of things that are O(n) in latency and O(n^2) in chip area/power - both instruction boundary detection and micro-op scheduling (since instructions can emit more than one uop) are included here. This isn't too bad when n is 4, but it has stressed both AMD and Intel's capabilities to make it to 8, and I don't think anyone would ever seriously consider building a 16-wide x86 machine. Once memory and I/O buses get fast enough to feed a 16-wide general-purpose computer, x86 as an architecture is in trouble. They have quietly gotten fast enough to feed an 8-wide machine. LPDDR4 very quietly took the speed crown from DDR4 due to the fact that the signal integrity problems are less demanding (soldered vs DIMM being the standard interface), and it looks like the DDR interface may be near the end of its useful life. Transceiver-based memory modules using standards like CXL and CCIX may be the long-term fix to the problems of DDR4. In the short-term, those are going to hurt, but long-term they should be a lot better.
- gpderetta 6y ago
  Common knowledge is that going wider quickly hits diminishing returns so generally there hasn't been a lot of pressure for x86 to go wider. It seems to be working for Apple though possibly because they are targeting differen trade offs (lower clock speed for example); but maybe their secret is a better modelling of common workloads revealing this common knowledge to be outdated.
  - ece 6y ago
    I'd like to see this explored more. I think AMD/Intel might be historically looking at C++/compiled workloads more than JS/Java/python interpreted workloads. JITs very well could take better advantage of wider cores than compiled code. Diminishing returns with increasing cache sizes and going wider doesn't seem to hold back the M1.
    - gpderetta 6y ago
      Maybe. JITs and runtimes in general might add some "overhead" code that does book-keeping and verifies assumptions (to rollback conditional optimistic optimizations). Maybe wider engines allow running this overhead without impacting actual runtime. It probably also help hide the cost of type checks and bound checks.
      - ece 6y ago
        It might just be the combination of better branch prediction, TSMC 5nm, 8-channel memory, 16k pages, along with 8-wide cores+larger structures especially cache are enough to account for the more perf/watt of the M1.
OldHand2018 6y ago
> The author seems to think Intel or AMD cannot make SoCs because of their business model. You gave a good example of AMD, but Intel has been making the Xeon-D SoC for a while now. They've always looked interesting to me, but outside of expensive SuperMicro motherboards, I've never seen one available to the general public. I think you are right though - both AMD and Intel would love it if vendors demanded high-performance SoCs. https://en.wikipedia.org/wiki/Xeon_D https://en.wikipedia.org/wiki/Xeon_D
- toast0 6y ago
  fwiw, I think Intel declared the Xeon-D line dead. They're not planning anything new there. That said, I don't think they would need much to make a Core series processor into a SoC; the chip does almost everything you'd need already; memory, some of the pci-e, (some) usb, (some) sata, legacy IO are already in the CPU for both Intel and AMD, and both offer chips with GPUs on board too. AMD has a 'chipless' chipset available for ryzen, the A300, it even has a new performance version, the X300. There's still plenty of other chips on the board, but there's nothing that's really a chipset.
  - OldHand2018 6y ago
    That's really disappointing, but entirely unsurprising. It seems that the "market" doesn't ever want anything new, unless someone hits them on the head it. Like what Apple just did. The neural engine and DSP on-chip are actually what I find most interesting about the Apple chip. It would be nice to see that start to happen with other manufacturers.
klelatti 6y ago
On 1) I think that you're right about the impact of the ISA being overdone but lets not forget that Intel has had a process advantage for a long time and that it was partly the volume of consumer sales that supported their R&D and helped them win on servers. That situation has changed now - the process advantage has gone and there is lots of money pouring into TSMC and the mobile SoC designers. For me the key point on the ISA is that Arm is not limited to two companies: what we've seen in other markets will happen in desktops and servers - the really big customers can take the ISA and build highly competitive SoCs that suit them on the leading process technology and for lower cost.
jsmith45 6y ago
By what measure are modern AMD CPUs not an SOC (especially the APU models)? They literally can function without a chipset. The chipsets are little more a PCI-E extender with some built in USB and SATA controllers connected to it. The CPUs do perform some form of handshaking with the chipset, but after that is done, it does not care. This handshake is literally about being able to lock out certain on die features if you don't buy the more expensive chipsets. (Or partner with AMD to get access to an small 8 pin activator chip to unlock the features you need, and add your own PCI-E extender if desired).
- spamizbad 6y ago
  I agree but I think the author is using a different standard and I’m saying AMD and Intel already meet that standard.

pclmulqdq 6y ago

The Intel ISA has some very powerful instructions that allow it to keep performance up, but unfortunately decoding n x86 instructions involves doing a number of things that are O(n) in latency and O(n^2) in chip area/power - both instruction boundary detection and micro-op scheduling (since instructions can emit more than one uop) are included here. This isn't too bad when n is 4, but it has stressed both AMD and Intel's capabilities to make it to 8, and I don't think anyone would ever seriously consider building a 16-wide x86 machine. Once memory and I/O buses get fast enough to feed a 16-wide general-purpose computer, x86 as an architecture is in trouble. They have quietly gotten fast enough to feed an 8-wide machine. LPDDR4 very quietly took the speed crown from DDR4 due to the fact that the signal integrity problems are less demanding (soldered vs DIMM being the standard interface), and it looks like the DDR interface may be near the end of its useful life. Transceiver-based memory modules using standards like CXL and CCIX may be the long-term fix to the problems of DDR4. In the short-term, those are going to hurt, but long-term they should be a lot better.

gpderetta 6y ago
Common knowledge is that going wider quickly hits diminishing returns so generally there hasn't been a lot of pressure for x86 to go wider. It seems to be working for Apple though possibly because they are targeting differen trade offs (lower clock speed for example); but maybe their secret is a better modelling of common workloads revealing this common knowledge to be outdated.
- ece 6y ago
  I'd like to see this explored more. I think AMD/Intel might be historically looking at C++/compiled workloads more than JS/Java/python interpreted workloads. JITs very well could take better advantage of wider cores than compiled code. Diminishing returns with increasing cache sizes and going wider doesn't seem to hold back the M1.
  - gpderetta 6y ago
    Maybe. JITs and runtimes in general might add some "overhead" code that does book-keeping and verifies assumptions (to rollback conditional optimistic optimizations). Maybe wider engines allow running this overhead without impacting actual runtime. It probably also help hide the cost of type checks and bound checks.
    - ece 6y ago
      It might just be the combination of better branch prediction, TSMC 5nm, 8-channel memory, 16k pages, along with 8-wide cores+larger structures especially cache are enough to account for the more perf/watt of the M1.

OldHand2018 6y ago

> The author seems to think Intel or AMD cannot make SoCs because of their business model. You gave a good example of AMD, but Intel has been making the Xeon-D SoC for a while now. They've always looked interesting to me, but outside of expensive SuperMicro motherboards, I've never seen one available to the general public. I think you are right though - both AMD and Intel would love it if vendors demanded high-performance SoCs. https://en.wikipedia.org/wiki/Xeon_D https://en.wikipedia.org/wiki/Xeon_D

toast0 6y ago
fwiw, I think Intel declared the Xeon-D line dead. They're not planning anything new there. That said, I don't think they would need much to make a Core series processor into a SoC; the chip does almost everything you'd need already; memory, some of the pci-e, (some) usb, (some) sata, legacy IO are already in the CPU for both Intel and AMD, and both offer chips with GPUs on board too. AMD has a 'chipless' chipset available for ryzen, the A300, it even has a new performance version, the X300. There's still plenty of other chips on the board, but there's nothing that's really a chipset.
- OldHand2018 6y ago
  That's really disappointing, but entirely unsurprising. It seems that the "market" doesn't ever want anything new, unless someone hits them on the head it. Like what Apple just did. The neural engine and DSP on-chip are actually what I find most interesting about the Apple chip. It would be nice to see that start to happen with other manufacturers.

klelatti 6y ago

On 1) I think that you're right about the impact of the ISA being overdone but lets not forget that Intel has had a process advantage for a long time and that it was partly the volume of consumer sales that supported their R&D and helped them win on servers. That situation has changed now - the process advantage has gone and there is lots of money pouring into TSMC and the mobile SoC designers. For me the key point on the ISA is that Arm is not limited to two companies: what we've seen in other markets will happen in desktops and servers - the really big customers can take the ISA and build highly competitive SoCs that suit them on the leading process technology and for lower cost.

jsmith45 6y ago

By what measure are modern AMD CPUs not an SOC (especially the APU models)? They literally can function without a chipset. The chipsets are little more a PCI-E extender with some built in USB and SATA controllers connected to it. The CPUs do perform some form of handshaking with the chipset, but after that is done, it does not care. This handshake is literally about being able to lock out certain on die features if you don't buy the more expensive chipsets. (Or partner with AMD to get access to an small 8 pin activator chip to unlock the features you need, and add your own PCI-E extender if desired).

spamizbad 6y ago
I agree but I think the author is using a different standard and I’m saying AMD and Intel already meet that standard.