4 ms·
> LPDDR4x is 32-bits per channel, 4x channels per chip DDR4 bus width is 64 bits per channel. Are you saying DIMMs include a sufficiently fast and complex cont
by Const-me 6y ago
> LPDDR4x is 32-bits per channel, 4x channels per chip
DDR4 bus width is 64 bits per channel. Are you saying DIMMs include a sufficiently fast and complex controller chip?
- dragontamer 6y agoClearly, this discussion has proven that I'm a bit out of my area here. But my understanding is that LPDDR4 have multiplie dies of RAM stacked on top of a chip. There's only two RAM chips on the Apple M1. https://upload.wikimedia.org/wikipedia/commons/8/83/Apple_M1.jpg https://upload.wikimedia.org/wikipedia/commons/8/83/Apple_M1... You can clearly see the two LPDDR4x chips packaged with the Apple M1. There's no question that the M1 package contains two DRAM chips. The only question is the configuration of the "insides" of these DRAM chips. ------ Anandtech's interviews give us a preview: 128-bit wide bus (8 x 16-bit it seems), two chips, LPDDR4x protocol. The details beyond that are pure speculation on my part.