3 ms·
Most of DRAM latency is actually not DRAM itself, but CPU, and its controller. DRAM always been at aroun 10-20ns of latency. PCB traces themselves add a maximu
by baybal2 6y ago
Most of DRAM latency is actually not DRAM itself, but CPU, and its controller.
DRAM always been at aroun 10-20ns of latency. PCB traces themselves add a maximum of 6ns roundtrip.
DDR PHYs on both sides do huge amounts of analog, and digital signal conditioning. Refresh system add random latency if you hit a refresh cycle. Prefetch-burst mechanism also adds limits of your effective random access times.
This is why HBM may well beat regular DDR on real world latencies.
- sliken 6y agoInteresting, thanks for the detailed info. I've done a fair number of benchmarking of different CPU architectures and never seen a latency lower than 60ns or so. My jaw dropped when I saw the M1 chasing pointers on large random array (much bigger than cache) at 30ns or so. That's a pretty amazing latency for l1 cache miss, l2 cache miss, and retrieving a cache line from main memory.