4 ms·
After looking at Apple's bandwidth (68GB/sec or so) and latency (random latency 32ns or so, if TLB friendly) I think it's time to consider ditching dimms. Half
by sliken 6y ago
After looking at Apple's bandwidth (68GB/sec or so) and latency (random latency 32ns or so, if TLB friendly) I think it's time to consider ditching dimms. Half the latency, higher bandwidth, and lower costs sounds good to me. Just hope that future motherboard makers with LPDDR4x-4266 have motherboard options with 32GB ram instead of today's rather low limit of 16GB on the M1.
- headmelted 6y agoI don’t know that there’s an architecture limit that means that higher than 16GB is infeasible. I suspect we’ll see 32gb in the new iMacs and presumably a lot more than that in the next Mac Pro (which I’m really excited about in terms of how they scale the architecture).
- baybal2 6y agoMost of DRAM latency is actually not DRAM itself, but CPU, and its controller. DRAM always been at aroun 10-20ns of latency. PCB traces themselves add a maximum of 6ns roundtrip. DDR PHYs on both sides do huge amounts of analog, and digital signal conditioning. Refresh system add random latency if you hit a refresh cycle. Prefetch-burst mechanism also adds limits of your effective random access times. This is why HBM may well beat regular DDR on real world latencies.
- sliken 6y agoInteresting, thanks for the detailed info. I've done a fair number of benchmarking of different CPU architectures and never seen a latency lower than 60ns or so. My jaw dropped when I saw the M1 chasing pointers on large random array (much bigger than cache) at 30ns or so. That's a pretty amazing latency for l1 cache miss, l2 cache miss, and retrieving a cache line from main memory.