3 ms·
Coming from discrete logic, a 5 transistor DRAM cell looks strange to me.. the good old “bistable multivibrator” circuit is just 2 transistors (and a few resist
by theamk 6y ago
Coming from discrete logic, a 5 transistor DRAM cell looks strange to me.. the good old “bistable multivibrator” circuit is just 2 transistors (and a few resistors, but I bet many of them could be eliminated with creative transitor sizing)
I am going to guess this design is better in terms of power consumption or total area?
- kens 6y agoThe cell design strikes me as strange too. According to the patent, static cells require "excessive space", refresh is inconvenient, and previous self-refreshing cells can accumulate erroneous charge. The patent claims all sorts of advantages of minimizing clock voltages, minimizing vias, using a single address line and single data line, etc. My interpretation is that in the pre-CMOS days, a static cell used too much power due to the load resistor. (The Intel 4004 and 8008 used dynamic storage for registers.) They didn't want to implement a counter for stepping through refresh addresses, so they developed this cell. (How much did they not want to implement a counter? The program counter is actually a linear-feedback shift register, so it steps through addresses in a pseudo-random order. This saved a few transistors compared to a real counter. The trick is you permute the data in ROM according to the same pattern and everything works just like you had a normal program counter.) https://patents.google.com/patent/US3876993A https://patents.google.com/patent/US3876993A
- dboreham 6y agoAccording to the patent, the primary benefit is self-refresh, and doing so avoiding substrate charge pump effects.