5 ms·
Reverse engineering RAM storage in early Texas Instruments calculator chips
- kens 6y agoAuthor here if anyone wants to discuss TI microcontrollers or RAM :-)
- colejohnson66 6y agoOff topic, but I never fail to see you post these comments on links to your blog. But you’re not the one posting the link, so how do you know when one is posted? Btw: I love reading these posts. It’s amazing how intricate these tiny things can be!
- kens 6y agoWell, I check HN a lot :-) But also I use f5bot.com, a free service that lets me know if I'm mentioned on reddit or HN. You give it a list of keywords and it emails you if they appear.
- johnisgood 6y agoI just want to ask if anyone here still writes code in Forth or not. :D
- parsecs 6y agoNot Ken but I've made a few projects with eForth for STM8 if that counts
- theamk 6y agoComing from discrete logic, a 5 transistor DRAM cell looks strange to me.. the good old “bistable multivibrator” circuit is just 2 transistors (and a few resistors, but I bet many of them could be eliminated with creative transitor sizing) I am going to guess this design is better in terms of power consumption or total area?
- kens 6y agoThe cell design strikes me as strange too. According to the patent, static cells require "excessive space", refresh is inconvenient, and previous self-refreshing cells can accumulate erroneous charge. The patent claims all sorts of advantages of minimizing clock voltages, minimizing vias, using a single address line and single data line, etc. My interpretation is that in the pre-CMOS days, a static cell used too much power due to the load resistor. (The Intel 4004 and 8008 used dynamic storage for registers.) They didn't want to implement a counter for stepping through refresh addresses, so they developed this cell. (How much did they not want to implement a counter? The program counter is actually a linear-feedback shift register, so it steps through addresses in a pseudo-random order. This saved a few transistors compared to a real counter. The trick is you permute the data in ROM according to the same pattern and everything works just like you had a normal program counter.) https://patents.google.com/patent/US3876993A https://patents.google.com/patent/US3876993A
- dboreham 6y agoAccording to the patent, the primary benefit is self-refresh, and doing so avoiding substrate charge pump effects.
- dboreham 6y agoIf you're looking for suggestions for chips to analyze (unlikely, I realize), a shout out for early 16-bit GI CPUs (so obscure that Google fails to remind me+ of the part#s), or the failed Nat Semi 32-bit chips such as the NS16032 or perhaps the "Basic-on-chip" NS8070. +Google knows about the CP-1600 but I'm thinking about an earlier design that wasn't single-chip.
- kens 6y agoThose chips are probably a bit too obscure for me :-) I tried to figure out what General Instruments CPU you are describing, but the CP-1600 is the only one I could come up with.