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Serious question, since I only have a little experience writing assembly: How would optimized M1 assembly differ from optimized ARM assembly in general? I ima

Serious question, since I only have a little experience writing assembly: How would optimized M1 assembly differ from optimized ARM assembly in general? I imagine good ARM assembly code on a Gravitron2 or a Snapdragon chip would be similarly good on an M1 chip

saagarjha 6y ago
There are always microarchitectural differences you can take advantage of, but Apple probably wants you to stick to the ISA as these things change in ways they don't want to document. Apple of course uses these things in the lower levels of their software, so if you're using their APIs you're getting this for free across OSes and CPUs.
cataphract 6y ago
The costs of different operations differ between CPUs that implement the same instruction set. Compilers have costs tables for each processor family for when you target them (e.g. with -mtune)
rsynnott 6y ago
Micro-architectural differences. For instance, from the 386 to Pentium 3 (and on Athlon, I believe), shifting was cheap, due to the presence of a barrel shifter. This was dropped in the P4, and suddenly shifting was quite expensive (I think, though I’m not sure, that it may actually have come back in later P4s). That’s the sort of thing compiler writers need to know about.
- userbinator 6y ago
  The P4 was quite an anomaly[1] in the history of x86, optimised for clock speed at the expense of many other things. All the subsequent generations went back to the norm, with the exception of the Atom series, and even that one is not as unusual as the P4. [1] Even the family/model/stepping designation has an oddity: the 486 was family 4, the Pentium was family 5, and then everything from the Pentium II/III up to the latest Core series, as well as the Atoms, uses family 6; but the P4 was family 15.
mhh__ 6y ago
It really depends on the actual design of the processor. Some things like the instruction density and inlining heuristics translate from processor to processor, but the actual microarchitecture (rather than the ISA) determine what is "good" code from platform to platform e.g. Good instruction scheduling depends on how the CPU is designed.

saagarjha 6y ago

There are always microarchitectural differences you can take advantage of, but Apple probably wants you to stick to the ISA as these things change in ways they don't want to document. Apple of course uses these things in the lower levels of their software, so if you're using their APIs you're getting this for free across OSes and CPUs.

cataphract 6y ago

The costs of different operations differ between CPUs that implement the same instruction set. Compilers have costs tables for each processor family for when you target them (e.g. with -mtune)

rsynnott 6y ago

Micro-architectural differences. For instance, from the 386 to Pentium 3 (and on Athlon, I believe), shifting was cheap, due to the presence of a barrel shifter. This was dropped in the P4, and suddenly shifting was quite expensive (I think, though I’m not sure, that it may actually have come back in later P4s). That’s the sort of thing compiler writers need to know about.

userbinator 6y ago
The P4 was quite an anomaly[1] in the history of x86, optimised for clock speed at the expense of many other things. All the subsequent generations went back to the norm, with the exception of the Atom series, and even that one is not as unusual as the P4. [1] Even the family/model/stepping designation has an oddity: the 486 was family 4, the Pentium was family 5, and then everything from the Pentium II/III up to the latest Core series, as well as the Atoms, uses family 6; but the P4 was family 15.

mhh__ 6y ago

It really depends on the actual design of the processor. Some things like the instruction density and inlining heuristics translate from processor to processor, but the actual microarchitecture (rather than the ISA) determine what is "good" code from platform to platform e.g. Good instruction scheduling depends on how the CPU is designed.