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TSMC: SoIC
- blopeur 6y agoWhats, Whys and Hows of TXMS-SoIC : https://3dfabric.tsmc.com/english/dedicatedFoundry/technology/SoIC_inDepth.htm https://3dfabric.tsmc.com/english/dedicatedFoundry/technolog... Papers : * https://ieeexplore.ieee.org/document/8811194 https://ieeexplore.ieee.org/document/8811194 * https://ieeexplore.ieee.org/document/8776486 https://ieeexplore.ieee.org/document/8776486
- ajnin 6y agoToo bad they chose a name already taken by another very well established IC packaging technology : https://en.wikipedia.org/wiki/Small_outline_integrated_circuit https://en.wikipedia.org/wiki/Small_outline_integrated_circu...
- magicalhippo 6y agoSOIC is the external package though, not sure it'll be that confusing as many chips are typically packaged in many different packages.
- The_rationalist 6y agoCould this be used for the next generation of HBM?
- skohan 6y agoIs there a risk in one manufacturer seemingly getting so far ahead in terms of being able to deliver high-performance processors?
- deleted 6y ago[deleted]
- mlindner 6y agoIntel was there. If a company gets far ahead then they start to rest on their laurels and then competitors catch back up. It's cyclical.
- virtue3 6y agoI think what hurt intel in the long run was actually their fully integrated stack. They couldn't really sell fab time to other companies cuz they didn't have a good attempt at fabbing for 3rd parties. So they were only fabricating intel chips, that's not nearly as big of a business as TSMC. So basically, TSMC can keep their last 3+ gens of fabs open and making product, while intel couldn't really reap any benefit from keeping old process nodes open. AMD made a good call selling off global foundries when it was apparent they couldnt keep up with Intel even. I think the really rough issue here is what happens if China does try to take Taiwan (and this is not unrealistic as China has been more aggressive towards them recently). TSMC is now a strategic asset for the USA. We've been attempting to get them to build a fab in the states for exactly this reason.
- ENOTTY 6y agoIntel fabs plenty of stuff at the 22 nm node, including chipsets for their CPUs[1], RF and other analog uses[2], novel RAM technologies, and their Lakefield/Foreveros thing. Given Intel's expanding product portfolio, there's likely additional internal customers for older nodes. [1]: https://www.tomshardware.com/news/intel-14nm-shortage-h310c,37819.html https://www.tomshardware.com/news/intel-14nm-shortage-h310c,... [2]: https://ieeexplore.ieee.org/document/9075914 https://ieeexplore.ieee.org/document/9075914
- naringas 6y agoI wish all this technology were more accesible. but they gotta protect their trade secrets (I guess...). I've heard about something called 'dycryl process' (in chip photolitography) but it is not the kind of info that it's easily found, nor easily understood even if I could google for it.
- MangoCoffee 6y ago>I wish all this technology were more accesible. but they gotta protect their trade secrets (I guess...). open source their manufacturing process? everyone can get EUV machine and all the components to make chip. you figure out the better yield part or packaging like TSMC
- valusr 6y agoThey could give you all the recipes and steps, but a newcomer isn't going to make it due to the needed experience and expertise.
- imbusy111 6y agoI assume keeping the parts cool becomes a big issue. You get twice the amount of heat to dissipate within the same area. Or is there some workaround?
- ksec 6y agoNo Workaround AFAIK, the idea right now is not to stack compute die on top of each other but other things like SRAM or parts that uses little energy for both cost and space efficiency.
- neolefty 6y agoThe goals here are kind of sideways from heat dissipation. * Different parts from different processes — for example DRAM and CPU need different processes, so it doesn't work to put them on the same chip — this integration is a step closer than on-package. * Yield — if you really want sixteen cores, and you're pushing the edge of your process, your yield for perfect eight-core chiplets will be dramatically better than for a sixteen-core chip or chiplet. But yeah concentrating all that into multi-chip chip will also concentrate the heat.
- baybal2 6y ago> Or is there some workaround? Synthetic diamonds, heatspreaders in the package
- the8472 6y ago*Isotopically pure diamonds
- nynx 6y agoThe work around would be microfluidic coolers, which aren't production ready yet, I believe.
- intricatedetail 6y agoIt is like national security matter and relatively inexpensive when talking about nation's budget scale. Why countries don't make their own chips? Should this be in the realm of public companies just like healthcare or energy in some countries?
- qppo 6y agoThe US does recognize the strategic importance of semiconductor manufacturing and spends billions on it each year. Many devices for markets like aerospace and defense are only manufactured domestically. That said, the US has a defensive pact with Taiwan and to attack the island would be to start World War 3. It's not really inexpensive in terms of a budget when you look at the nations that could benefit from the investment as a national security concern. Look outside the US nuclear umbrella and NATO to nations not friendly with the PRC - who among them is wealthy enough to start a chip industry that can compete?
- hindsightbias 6y agoThere is no defensive pact with Taiwan. There will be no WW3 should the PRC decide to go for it.
- machinelabo 6y agoM1 chip has a bog standard Package-on-Package architecture - there is nothing special about it. The CoWoS and other 3D packaging technologies from TSMC's marketing pages aren't on the M1 chip. I believe there isn't even a silicon interposer due to cost presumably [1]. It is substrate on top of substrate (PoP) to connect the memory and CPU. CPU+GPU are on the same die which is pretty remarkable (Intel's IGPUs have been on the same die as well albeit they're not as powerful as M1s graphics) but that's somewhat unrelated to the packaging. Here is a good diagram (sans the silicon interposer): https://www.researchgate.net/figure/3D-stacked-DRAM-example-High-Bandwidth-Memory-consists-of-stacked-memory-layers-four_fig5_320867388 https://www.researchgate.net/figure/3D-stacked-DRAM-example-... Btw, memory has been stacked like that for a decade or more. Used to be stacked + wirebonded. But now, we have through-silicon vias (TSVs). The reason you can stack memory like that are many, one of them being thermals / power density. [1] https://www.youtube.com/watch?v=t6KUnC-oU5g https://www.youtube.com/watch?v=t6KUnC-oU5g
- ajarmst 6y agoWhoa! Blew through my marketing gibberish budget less than one paragraph in.