Intel has been at 5 decoders since Skylake (~2015). I'm not sure why everyone focuses on the decoders as the primary determinant of width. There are other bott

Intel has been at 5 decoders since Skylake (~2015). I'm not sure why everyone focuses on the decoders as the primary determinant of width. There are other bottlenecks which may be narrower than the decoders, and the decoders may not even be used when a uop cache or something like a "loop buffer" (LSD on Intel) is present. So AMD doesn't believe that wider chips aren't useful or that 4 is a limit, because they went to 5-wide in Zen (or 6, depending on how you count it) and I expect them to go wider in the future. Intel went from 4 wide (narrowest bottleneck) to 5 wide in Ice Lake. Wider chips are the future, and there is no "hard wall" at 4 for x86, just like any earlier width increase: just constantly diminishing returns.