3 ms·
Isn't it a switch because the weak memory model, whilst providing less guarantees is more performant?. So they are trying to have both the x86 mode which isn't
by _kbh_ 6y ago
Isn't it a switch because the weak memory model, whilst providing less guarantees is more performant?. So they are trying to have both the x86 mode which isn't as performant, but works a lot faster in hardware than the software implementation and the faster weaker ARM model.
- saagarjha 6y agoThe thing I mentioned should be better in that case since it’d enforce the right memory ordering on a per-instruction basis.
- neerajsi 6y agoThe ls/st instructions take a large amount of encoding space for all the addrmodes. I don't think the rcpc instructions and other acq/rel instructions were given the same encoding space.