5 ms·
I believe with regards to TSO, it is actually a huge benefit performance wise. Without you would need to effectively have a barrier after every memory operation
by _kbh_ 6y ago
I believe with regards to TSO, it is actually a huge benefit performance wise. Without you would need to effectively have a barrier after every memory operation ARM, reducing performance drastically.
- saagarjha 6y agoImplementing the memory ordering in hardware is a huge performance benefit, but they didn’t have to do it with a switch like they have right now. ARMv8.4-RCpc would be enough, and I believe M1 supports these too. (FWIW, Rosetta itself does “cheat”: the translated code and the runtime shares an address space, and memory accesses are not checked, so it’s possible to write an “Intel” binary that is aware of the runtime and can read emulator state.)
- _kbh_ 6y agoIsn't it a switch because the weak memory model, whilst providing less guarantees is more performant?. So they are trying to have both the x86 mode which isn't as performant, but works a lot faster in hardware than the software implementation and the faster weaker ARM model.
- saagarjha 6y agoThe thing I mentioned should be better in that case since it’d enforce the right memory ordering on a per-instruction basis.
- neerajsi 6y agoThe ls/st instructions take a large amount of encoding space for all the addrmodes. I don't think the rcpc instructions and other acq/rel instructions were given the same encoding space.