5 ms·
For an the references to this, I haven't yet seen a description of what the optimization is. Anyone know?
by spankalee 6y ago
For an the references to this, I haven't yet seen a description of what the optimization is. Anyone know?
- tambourine_man 6y agoIt’s much more than twice as fast. https://twitter.com/catfish_man/status/1326238434235568128?s=21 https://twitter.com/catfish_man/status/1326238434235568128?s...
- spankalee 6y agoWhat's the actual optimization though?
- tambourine_man 6y agoHave you read the tweet and thread? If so, I don’t understand what you’re asking.
- spankalee 6y agoTwitter wasn't making the relevant responses really visible. _kbh_ pointed it out
- plasma 6y agoThe tweet author in the linked thread later writes: "Weaker memory model makes acquire-release atomics possible to implement much more efficiently, in exchange for not hiding some classes of multithreading bugs"
- _kbh_ 6y agoI think I found the answer in this tweet. https://twitter.com/Catfish_Man/status/1326298205034696705 https://twitter.com/Catfish_Man/status/1326298205034696705 Heres a snipped quote. "this further improvement is because uncontended acquire-release atomics are about the same speed as regular load/store on A14"
- annilt 6y agox86 has total store order, all stores are queued(store buffer) in the CPU and then pushed to the cache subsystem. Last item has to wait previous ones. Arm doesn’t have TSO, so CPU can reorder stores in the queue or issue stores out of order etc. depending on memory barrier use.
- olliej 6y agoIf you read the Catfish_Man tweet, he says that even under rosetta refcounting is faster, and under rosetta M1 has TSO.