3 ms·
Finally I see somebody mentioning the memory ordering. I've been wondering for a while how they've managed to get multithreaded x86 emulation working fast. I ha
by messe 6y ago
Finally I see somebody mentioning the memory ordering. I've been wondering for a while how they've managed to get multithreaded x86 emulation working fast. I had heard mentions of "kernel support", but hadn't really looked into it much. It turns out that what I had guessed was correct, and that they simply added intel's memory ordering as an optional mode to their processor; "When running translated x86 code, they switch the mode of the CPU to conform to Intel's memory ordering."
- zozbot234 6y agoRISC-V also has a weak memory ordering by default, with TSO (like x86) as an optional feature. So this is not a novel approach in any way.
- monocasa 6y agoThere's a spec for that, but I don't know of any synthesizable RV cores with optional TSO that have actually been made, whether ASICs _or_ configurable logic. That does make it pretty novel on Apple's end. I agree with Heinlein that "a good idea is worth one bottle of scotch"; that the execution is where the vast majority of the work is and where the vast majority of praise should lie. And that's coming from someone who's not as bullish as some on Apple's execution. I think AMD's cores are better and compared 1/1 on the same process node Apple would look a little behind overall. But Apple for sure gets praise for their execution here (optionality in store order), which is remarkably good.
- brigade 6y agoWell sure, POWER7 implemented a strong-ordering mode specifically for x86 emulation a decade ago [1] [1] https://marc.info/?l=linux-mm&m=121382852909406&w=2 https://marc.info/?l=linux-mm&m=121382852909406&w=2