Generally caches, especially those using the full 8 transistors per cell instead of those trying to get by with 6, don't use all that much power. One obvious i

Generally caches, especially those using the full 8 transistors per cell instead of those trying to get by with 6, don't use all that much power. One obvious idea is to design a chip such that the hot logic layers are on top, right next to the heat sync, and the logic layers are underneath. 3D topology means that everything can effectively be closer together for lower latency and lower information transport energy but you can make the caches bigger at the same time. For true 3D chips that are more cube-like people talk about putting liquid cooling channels into the structure but that would be a technology for quite a ways off.