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Not a hardware engineer, but I've dabbled a bit with very basic CPU design using an open source Verilog compiler and simulator (specifically, Icarus Verilog). J

• pjc50 6y ago
  Support is a non-trivial benefit when mistakes or delays cost money. The feature set of proprietary EDA is huge, and the place & route optimisers have been tuned for years. Sure, it costs $250k for a Synopsys license with the full suite of tools; it also costs far more than that to have to redo a mask set, lose your slot in the fab's calendar, etc.
• rasz 6y ago
  Article is about tools for synthesizing ASICs, at least one layer deeper than FPGA.
• petermonsson 6y ago
  They offer productivity. Commercial tools have simulation speed and a half decent visual debugger for example. The bar is not that high, but Icarus is behind in these two areas
• doix 6y ago
  I work in the industry but don't have a perfect understanding of everything, hopefully someone will correct any mistakes in my explanation. So Icarus Verilog can only be used for simulation, you will never produce a physical chip using (only) this tool. I guess I'll quickly start with the end goal. Assuming you don't have your own fab and want to get something manufactured by one of the fabs, you'll most likely send them a GDS file[0]. It's basically a file that contains coordinates for a bunch of rectangles and their layer which define how the mask [1] should look like. How do you go from verilog to a GDS file? Well it's a pretty long process, none of the steps can be done with Icarus Verilog: 1. Synthesis, this will synthesize (coming from the software world, I guess you could call this "compile") your verilog into standard cells(imagine AND/NOT/OR gates) and how they are connected. * These standard cells come from a PDK[2](process design kit) which will be supplied to you by your semiconductor fab. I think if you wanted to break into the industry, supporting PDKs will be a pain. Allegedly there is OpenAccess[3] which is meant to allow for a "standard" way of developing these PDK's, but I'm not convinced. 2. Placement, your chip is a rectangle of a certain size (you decide the size, the bigger, the more expensive it'll be since wafters are fixed size) and it needs to fit all those standard cells. A tool will figure out how to optimally place them. There are certain rules it needs to follow defined by your PDK. 3. Routing, you've placed the cells on your chip, but they aren't connected. A tool will find an optimal?(maybe?) solution on how to connect the standard cells so that it matches the netlist generated in step 1. This pretty much gets you the GDS. 3.a. After everything has been routed, you can extract the physical properties from the layout and resimulate everything with the "real" design. When you were simulating with icarus verilog, it was just checking that the logic is sound. It didn't have any of the real world delays, with the extractd netlist, you can simulate it with the delays. I'm pretty sure Icarus Verilog would support this, I think the delays are just implemented with "`delay X" statements, but I might be wrong. Now this primarily deals with the "digital" part of the chip. Now I'm a bit unsure about this part, but I'm pretty sure you can't just make a "digital" (i.e verilog) only chip. I'm assuming at a bare minimum any product now days will have some ESD protection which will require at least a bit of custom. For the analogue part of the chip, it's completely separate form Icarus Verilog. Analog designers will be manually placing transistors to create circuits for the chip. The PDK will define how the transistors behave under different voltages/temperatures/process corners[4]. They will then simulate their circuit to see if it works. To go from the circuit they designed to the GDS, someone (a person) will go through the circuit and manually layout their circuit. There are tools that check that the manual layout process matches the schematic/circuit (LVS – layout vs schematic). There are a bunch of design rules that the fab will specify (DRC, design rule checks) that the layout needs to meet, there are tools which will check those for you. Basically, a bunch of tools and licenses you need to pay these vendors for. Normally someone will pull in the synthesized digital into the analogue layout to create the final GDS before it’s sent to the fab. I hope that gives you a peek into what’s involved in making these chips from a tools perspective. These EDA tool licenses are almost all token based and use FlexLm[5]. You're paying per instance of the tool running. Most of the simulations run in parallel and take multiple tokens. The licensing costs for these things go into multi-millions for any decently sized semi-conductor company. Apologizes in advance for any inaccuracies or any omissions. There's definitely a lot more stuff involved in the process, but the comment was getting really long already. notes: I've used verilog everywhere, but it might as well be VHDL or any other HDL. [0] https://en.wikipedia.org/wiki/GDSII https://en.wikipedia.org/wiki/GDSII [1] https://en.wikipedia.org/wiki/Photomask https://en.wikipedia.org/wiki/Photomask [2] https://en.wikipedia.org/wiki/Process_design_kit https://en.wikipedia.org/wiki/Process_design_kit [3] https://en.wikipedia.org/wiki/OpenAccess https://en.wikipedia.org/wiki/OpenAccess [4] https://en.wikipedia.org/wiki/Process_corners https://en.wikipedia.org/wiki/Process_corners [5] https://en.wikipedia.org/wiki/FlexNet_Publisher https://en.wikipedia.org/wiki/FlexNet_Publisher
  • f00zz 6y ago
    Thank you so much for the very interesting and detailed explanation!