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Intel needs to step up their game if they want to stay relevant. I am sure their execs know it so I can't wait to see what they will offer in the next 5 years.

by belval 6y ago

mhh__ 6y ago
Intel's revenue is big enough that they must have some kind of warchest to fall back on. Obviously money isn't everything but it doesn't hurt. They can probably still hammer AMD on both their software and documentation, i.e. roughly a quarter of their sales are to data centres. It will be interesting to see what happens to X86 post-M1 (i.e. ARM coming of age), I suspect not much but I think the world has changed enough to have another stab at VLIW (for example) even if the cost/benefit is pretty marginal.
- gabereiser 6y ago
  I’ll second this. My M1 Air is a freak of nature. I’m so excited for this next wave of computing. Lots of things that need setup Dev tooling wise and much work underway to get it supported but my god man... and it’s passively cooled. I have a beast i7 gaming rig too and my M1 beats it at everything but graphics performance. What I think Intel will continue to work their enterprise business until this “arm wave” starts to pull up. Engineers at Intel probably have some ideas.
  - deleted 6y ago
    [deleted]
  - mhh__ 6y ago
    I genuinely don't think M1 is a new wave of computing (yet), both in the sense that it's apple so it's not up to you what you do with it but also because ARM and X86 aren't all that different these days. Ultimately M1 is "Company with enough money to buy the US Navy, follows existing path to logical conclusion, succeeds". If a company other than apple makes a fast arm chip that'd be very interesting, though. Nvidia have probably thought about it.
    - josh2600 6y ago
      Time will tell if you're right. I do think that what's happening under the hood of the Apple chip is real and is causing more than a few executives in the silicon world to lose sleep. This reminds me of when RIM got their hands on an iPhone for the first time. One of many articles: https://appleinsider.com/articles/10/12/27/rim_thought_apple_was_lying_about_original_iphone_in_2007 https://appleinsider.com/articles/10/12/27/rim_thought_apple...
      - novok 6y ago
        I think it the hints were there if you were in the industry. CPU scaling is TPU scaling and apple's chips were showing leading single core performance compared to android / qualcomm chips for many years now with very low power usage. After that you could see how they could scale that up relatively easily. Also apple built in some special instructions that makes macOS software better, like core operations of objective-c, so some of this might be very apple runtime specific optimizations.
        tinus_hn 6y ago
        The first iPhones used generic Samsung processors and the power is quite similar to the hardware in BlackBerrys contemporary products. They probably just didn’t realize that one day of battery life is enough for most use cases and is less important than a real browser and the other features brought by the iPhone.
        josh2600 6y ago
        I feel like you're glossing over a bunch of things here. 1) the display on the iphone was gigantic compared to any other device on the market. The fact the iPhone had the battery life it did was amazing. 2) the software on the iphone destroyed anything RIM had ever put forward. 3) the iPhone was a much better piece of hardware aesthetically and performance-wise than anything RIM had ever put out. Their closest competitor was the Pearl and it was garbage compared to the iPhone. 4) Lastly, RIM had 10 year development cycles. Pivoting to attack the iPhone meant ripping apart 10 years of planned development much of which was already executed. Pivoting that hard is just not something companies at the scale or RIM are designed to do. RIM should've seen the writing on the wall, shred their hardware business, and gone all in on supporting BES on iPhone. I digress...
- sharpneli 6y ago
  The current CPU's already are VLIW in a fashion. Its just that they have a hardware jitter for it. That's what superscalar OoO CPU basically is, a piece of HW that generates VLIW instructions based on the normal instructions that come in. A superscalar execution port is basically just one subinstruction in VLIW. Explicit VLIW only helps you to save that piece of silicon from the chip. And it's not that much in the grand scheme of things. It used to be, but not anymore. Static compile time VLIW means one cannot really make it wider anymore, or narrower. Dynamically doing it on runtime means a cheaper and smaller core can just be narrower. Remove an instruction slot for one integer ALU? Fine, no issues. Everything still works, albeit slower by that much. Make a beefier chip? Perfect, it got faster by the amount of instruction level parallelism that was available. In addition a compiler cannot really see across function boundaries (except if it's statically determinable). A jitter can. Modern chips have reordering window of hundreds of instructions, M1 apparently goes up to over 600. That's quite a lot of stuff there that it can dynamically reorder across. A compiler might not have noticed that due to some weird dynamic call that was not visible during compilation time there is now an FPU instruction that could be inserted here, an OoO processor can. Due to that explicit VLIW is basically dead outside of some highly specific applications, like DPS and whatnot. In a similar fashion ridculously wide vector units were obsoleted by the approach pioneered by GPU's. Just add few things to allow masking based on branches and you get SIMT approach. Write as if it was scalar code and it'll run on HW that has vector lengths going from none at all up to whatever, NVidia has 32 wide vector units as an example.
  - jleahy 6y ago
    Even more importantly, and I'm surprised you didn't mention it, static compile time VLIW doesn't know what to do for memory access. A load might take any number of cycles depending on whether the line is in L1, L2 or L3 cache, with static compile time VLIW then the compiler has to guess, if it's optimistic the whole CPU stalls, if it's pessimistic then you're much slower than you would otherwise be. I believe this is the real thing that make superscalar OoO (ie. JIT to VLIW in silicon) win.
    - sharpneli 6y ago
      That's a great point to emphasize. Because memory access times are inherently more or less nondeterministic. I consider it to be roughly as important as being able to reorder instructions across non statically determined branches and function calls. And both of these expose the fundamental weakness in explicit VLIW, if it's essentially nondeterministic it cannot be taken advantage of. Then we naturally have some other benefits, like hyperthreading. Which basically is just compiling two instruction streams together on the fly.
topspin 6y ago
The trial balloons currently being floated by Intel forgo the pursuit of cutting edge process nodes in favor of third party fabs. Intel's existing foundries will serve older nodes while external foundries will build the high margin devices. They've been carefully dropping hints of this since July. Through the first week of November the headlines were "Intel to decide soon" whether to outsource, with a decision supposedly appearing sometime in January. This looks like the sort of precision expectation setting one would expect of an experienced zombie corp CEO like Swan. So don't bet on Intel making any great comeback in fab tech; they've decided they can be 'relevant' without it.
- petra 6y ago
  Since Intel mostly fabs it's own chips, what will it serve with older nodes ? And will that be enough ?
- JackMcMack 6y ago
  It will not be enough. There are essentially 3 leading fabs left: TSMC, Samsung, Intel. Samsung has yield issues, Intel has yield issues, TSMC somehow has no issues. GlobalFoundries has already dropped out of the race. TSMC is selling every wafer they make, and continues to invest heavily to solidify it's lead. ALL of these fabs depend on ASML machines. IIRC last year they delivered just over half of the machines that were ordered.
  - deleted 6y ago
    [deleted]
  - novok 6y ago
    If all of these fabs rely on ASML machines, why does TSMC have its shit together while the other two do not?
    - londons_explore 6y ago
      I think in 50 years we will find out that various state security services have been interfering with IC fabrication tech. Things like deliberately moving critical things by a few nanometers so entire production runs are broken...
websg-x 6y ago
Intel already got 'Foveros 3D Chip Stacking’ Tech shipping last June, the Lakefield processor.
hinkley 6y ago
We know that some components of a chip benefit more from die shrinkage than others. Intel is having yield problems with die shrinkage. Chiplets are a thing. I can’t for the life of me figure out why Intel hasn’t already hedged their bets and started working hard on hybrid chips. Especially since this now appears to be a long term industry direction. If the next step blunts the consequences of your current problems, why not jump on it? Sunk cost fallacy?
- tambre 6y ago
  Intel has EMIB [0], which they've used in i7-8809G [1]. And they seem to be going all-in on chiplets heavily... for 7nm [2]. At their current pace it'll be a few years before that. [0] https://www.intel.com/content/www/us/en/foundry/emib.html https://www.intel.com/content/www/us/en/foundry/emib.html [1] https://en.wikichip.org/wiki/intel/core_i7/i7-8809g https://en.wikichip.org/wiki/intel/core_i7/i7-8809g [2] https://www.anandtech.com/show/16021/intel-moving-to-chiplets-client-20-for-7nm https://www.anandtech.com/show/16021/intel-moving-to-chiplet...
jonplackett 6y ago
I wonder how much better Intel's i9 laptop chips would perform if they were on 5nm like the M1. Would they be competitive? Or are apple so much further ahead on other things too?

Intel needs to step up their game if they want to stay relevant. I am sure their execs know it so I can't wait to see what they will offer in the next 5 years.

by belval 6y ago

Intel needs to step up their game if they want to stay relevant. I am sure their execs know it so I can't wait to see what they will offer in the next 5 years.

mhh__ 6y ago

Intel's revenue is big enough that they must have some kind of warchest to fall back on. Obviously money isn't everything but it doesn't hurt. They can probably still hammer AMD on both their software and documentation, i.e. roughly a quarter of their sales are to data centres. It will be interesting to see what happens to X86 post-M1 (i.e. ARM coming of age), I suspect not much but I think the world has changed enough to have another stab at VLIW (for example) even if the cost/benefit is pretty marginal.

gabereiser 6y ago
I’ll second this. My M1 Air is a freak of nature. I’m so excited for this next wave of computing. Lots of things that need setup Dev tooling wise and much work underway to get it supported but my god man... and it’s passively cooled. I have a beast i7 gaming rig too and my M1 beats it at everything but graphics performance. What I think Intel will continue to work their enterprise business until this “arm wave” starts to pull up. Engineers at Intel probably have some ideas.
- deleted 6y ago
  [deleted]
- mhh__ 6y ago
  I genuinely don't think M1 is a new wave of computing (yet), both in the sense that it's apple so it's not up to you what you do with it but also because ARM and X86 aren't all that different these days. Ultimately M1 is "Company with enough money to buy the US Navy, follows existing path to logical conclusion, succeeds". If a company other than apple makes a fast arm chip that'd be very interesting, though. Nvidia have probably thought about it.
  - josh2600 6y ago
    Time will tell if you're right. I do think that what's happening under the hood of the Apple chip is real and is causing more than a few executives in the silicon world to lose sleep. This reminds me of when RIM got their hands on an iPhone for the first time. One of many articles: https://appleinsider.com/articles/10/12/27/rim_thought_apple_was_lying_about_original_iphone_in_2007 https://appleinsider.com/articles/10/12/27/rim_thought_apple...
    - novok 6y ago
      I think it the hints were there if you were in the industry. CPU scaling is TPU scaling and apple's chips were showing leading single core performance compared to android / qualcomm chips for many years now with very low power usage. After that you could see how they could scale that up relatively easily. Also apple built in some special instructions that makes macOS software better, like core operations of objective-c, so some of this might be very apple runtime specific optimizations.
      - tinus_hn 6y ago
        The first iPhones used generic Samsung processors and the power is quite similar to the hardware in BlackBerrys contemporary products. They probably just didn’t realize that one day of battery life is enough for most use cases and is less important than a real browser and the other features brought by the iPhone.
        josh2600 6y ago
        I feel like you're glossing over a bunch of things here. 1) the display on the iphone was gigantic compared to any other device on the market. The fact the iPhone had the battery life it did was amazing. 2) the software on the iphone destroyed anything RIM had ever put forward. 3) the iPhone was a much better piece of hardware aesthetically and performance-wise than anything RIM had ever put out. Their closest competitor was the Pearl and it was garbage compared to the iPhone. 4) Lastly, RIM had 10 year development cycles. Pivoting to attack the iPhone meant ripping apart 10 years of planned development much of which was already executed. Pivoting that hard is just not something companies at the scale or RIM are designed to do. RIM should've seen the writing on the wall, shred their hardware business, and gone all in on supporting BES on iPhone. I digress...
sharpneli 6y ago
The current CPU's already are VLIW in a fashion. Its just that they have a hardware jitter for it. That's what superscalar OoO CPU basically is, a piece of HW that generates VLIW instructions based on the normal instructions that come in. A superscalar execution port is basically just one subinstruction in VLIW. Explicit VLIW only helps you to save that piece of silicon from the chip. And it's not that much in the grand scheme of things. It used to be, but not anymore. Static compile time VLIW means one cannot really make it wider anymore, or narrower. Dynamically doing it on runtime means a cheaper and smaller core can just be narrower. Remove an instruction slot for one integer ALU? Fine, no issues. Everything still works, albeit slower by that much. Make a beefier chip? Perfect, it got faster by the amount of instruction level parallelism that was available. In addition a compiler cannot really see across function boundaries (except if it's statically determinable). A jitter can. Modern chips have reordering window of hundreds of instructions, M1 apparently goes up to over 600. That's quite a lot of stuff there that it can dynamically reorder across. A compiler might not have noticed that due to some weird dynamic call that was not visible during compilation time there is now an FPU instruction that could be inserted here, an OoO processor can. Due to that explicit VLIW is basically dead outside of some highly specific applications, like DPS and whatnot. In a similar fashion ridculously wide vector units were obsoleted by the approach pioneered by GPU's. Just add few things to allow masking based on branches and you get SIMT approach. Write as if it was scalar code and it'll run on HW that has vector lengths going from none at all up to whatever, NVidia has 32 wide vector units as an example.
- jleahy 6y ago
  Even more importantly, and I'm surprised you didn't mention it, static compile time VLIW doesn't know what to do for memory access. A load might take any number of cycles depending on whether the line is in L1, L2 or L3 cache, with static compile time VLIW then the compiler has to guess, if it's optimistic the whole CPU stalls, if it's pessimistic then you're much slower than you would otherwise be. I believe this is the real thing that make superscalar OoO (ie. JIT to VLIW in silicon) win.
  - sharpneli 6y ago
    That's a great point to emphasize. Because memory access times are inherently more or less nondeterministic. I consider it to be roughly as important as being able to reorder instructions across non statically determined branches and function calls. And both of these expose the fundamental weakness in explicit VLIW, if it's essentially nondeterministic it cannot be taken advantage of. Then we naturally have some other benefits, like hyperthreading. Which basically is just compiling two instruction streams together on the fly.

topspin 6y ago

The trial balloons currently being floated by Intel forgo the pursuit of cutting edge process nodes in favor of third party fabs. Intel's existing foundries will serve older nodes while external foundries will build the high margin devices. They've been carefully dropping hints of this since July. Through the first week of November the headlines were "Intel to decide soon" whether to outsource, with a decision supposedly appearing sometime in January. This looks like the sort of precision expectation setting one would expect of an experienced zombie corp CEO like Swan. So don't bet on Intel making any great comeback in fab tech; they've decided they can be 'relevant' without it.

petra 6y ago
Since Intel mostly fabs it's own chips, what will it serve with older nodes ? And will that be enough ?
JackMcMack 6y ago
It will not be enough. There are essentially 3 leading fabs left: TSMC, Samsung, Intel. Samsung has yield issues, Intel has yield issues, TSMC somehow has no issues. GlobalFoundries has already dropped out of the race. TSMC is selling every wafer they make, and continues to invest heavily to solidify it's lead. ALL of these fabs depend on ASML machines. IIRC last year they delivered just over half of the machines that were ordered.
- deleted 6y ago
  [deleted]
- novok 6y ago
  If all of these fabs rely on ASML machines, why does TSMC have its shit together while the other two do not?
  - londons_explore 6y ago
    I think in 50 years we will find out that various state security services have been interfering with IC fabrication tech. Things like deliberately moving critical things by a few nanometers so entire production runs are broken...

websg-x 6y ago

Intel already got 'Foveros 3D Chip Stacking’ Tech shipping last June, the Lakefield processor.

hinkley 6y ago

We know that some components of a chip benefit more from die shrinkage than others. Intel is having yield problems with die shrinkage. Chiplets are a thing. I can’t for the life of me figure out why Intel hasn’t already hedged their bets and started working hard on hybrid chips. Especially since this now appears to be a long term industry direction. If the next step blunts the consequences of your current problems, why not jump on it? Sunk cost fallacy?

tambre 6y ago
Intel has EMIB [0], which they've used in i7-8809G [1]. And they seem to be going all-in on chiplets heavily... for 7nm [2]. At their current pace it'll be a few years before that. [0] https://www.intel.com/content/www/us/en/foundry/emib.html https://www.intel.com/content/www/us/en/foundry/emib.html [1] https://en.wikichip.org/wiki/intel/core_i7/i7-8809g https://en.wikichip.org/wiki/intel/core_i7/i7-8809g [2] https://www.anandtech.com/show/16021/intel-moving-to-chiplets-client-20-for-7nm https://www.anandtech.com/show/16021/intel-moving-to-chiplet...

jonplackett 6y ago

I wonder how much better Intel's i9 laptop chips would perform if they were on 5nm like the M1. Would they be competitive? Or are apple so much further ahead on other things too?