5 ms·

Generally speaking you can choose either power efficiency or a wide bus, but rarely both. If you want a crappy underpowered m.2 slot, probably Intel Atom is the

Generally speaking you can choose either power efficiency or a wide bus, but rarely both. If you want a crappy underpowered m.2 slot, probably Intel Atom is the cheapest route. High performance ARM with m.2 PCI, not sure, but guessing if it's around it probably isn't cheap

lifty 6y ago
Yeah, that makes sense. I wouldn't expect the same price point as an RPi and would love a higher performance CPU, but I think they are not out there at the moment. Wouldn't mind having something like 8 graviton2 cores and an nvme slot :)
throwaway894345 6y ago
Let's say one has a friend who doesn't know what "a wide bus" refers to... What would be a good way of explaining it to said friend?
- othercharles 6y ago
  A single PCIe lane can draw 0.5 A, 4x rises to 2 A. Separately, (random top Google result cutpaste): Architectural-level power optimization can target different system components such as CPU, caches, main memory,and buses [5, 6, 22, 4]. Power spent in off-chip buses can be a significant portion of the overall power budget. As an example, the core power consumption of Intel Celeron at 266MHz is 16W, while its off-chip bus (for a standard configuration) operating at 133 MHz consumes 3.3W [12, 13]. The contribution of off-chip bus power consumption to the overall power budget increases even more for embedded systems with low-power processor cores and memories, making off-chip buses a potential candidate for power optimization. Figure 1 shows the power consumption due to off-chip data bus for several embedded benchmark codes as a percentage of the overall power consumption (which includes processor data path, caches, buses, TLB, register file, instruction issue logic, clock, and off-chip memory) for an embedded processor. From this figure, we see that the off-chip data bus consumes between 9.8% and 23.2% of the total power consumed by the system depending on the benchmark being run. So, reducing the power consumption of the off-chip data bus would reduce the overall power consumption of the system to a considerable extent
- mixmastamyk 6y ago
  More lanes on the freeway.

lifty 6y ago

Yeah, that makes sense. I wouldn't expect the same price point as an RPi and would love a higher performance CPU, but I think they are not out there at the moment. Wouldn't mind having something like 8 graviton2 cores and an nvme slot :)

throwaway894345 6y ago

Let's say one has a friend who doesn't know what "a wide bus" refers to... What would be a good way of explaining it to said friend?

othercharles 6y ago
A single PCIe lane can draw 0.5 A, 4x rises to 2 A. Separately, (random top Google result cutpaste): Architectural-level power optimization can target different system components such as CPU, caches, main memory,and buses [5, 6, 22, 4]. Power spent in off-chip buses can be a significant portion of the overall power budget. As an example, the core power consumption of Intel Celeron at 266MHz is 16W, while its off-chip bus (for a standard configuration) operating at 133 MHz consumes 3.3W [12, 13]. The contribution of off-chip bus power consumption to the overall power budget increases even more for embedded systems with low-power processor cores and memories, making off-chip buses a potential candidate for power optimization. Figure 1 shows the power consumption due to off-chip data bus for several embedded benchmark codes as a percentage of the overall power consumption (which includes processor data path, caches, buses, TLB, register file, instruction issue logic, clock, and off-chip memory) for an embedded processor. From this figure, we see that the off-chip data bus consumes between 9.8% and 23.2% of the total power consumed by the system depending on the benchmark being run. So, reducing the power consumption of the off-chip data bus would reduce the overall power consumption of the system to a considerable extent
mixmastamyk 6y ago
More lanes on the freeway.