3 ms·

This time around it’s not a pure software solution. ARM has a significantly weaker memory model than x86, which makes translation generally difficult and/or slo

This time around it’s not a pure software solution. ARM has a significantly weaker memory model than x86, which makes translation generally difficult and/or slow. It appears the M1 natively supports the x86 memory model which makes the rest of the task substantially easier.

spijdar 6y ago
This actually isn't new -- POWER processors have this exact same hardware support for emulating x86. It was even present until (the unreleased) POWER10. POWER chips up to and including 9 support "SAO", Strong Access Ordering mode. It is mentioned in exactly one sentence in the CPU manual: "The POWER9 core supports the SAO mode defined in Power ISA." This feature appears to solely have existed for QuickTransit's translation software, as POWER has a weaker memory model than x86. Linux briefly mentions this in the man (2) page for mprotect, stating: PROT_SAO (since Linux 2.6.26) The memory should have strong access ordering. This feature is specific to the PowerPC architecture (version 2.06 of the architecture specification adds the SAO CPU feature, and it is available on POWER 7 or PowerPC A2, for example).