5 ms·
Nice. The XTensa cores always felt weird. Too bad they only included the I/M/C extensions - no floats, vectors, or atomics. And USB would be nice (nevermind, i
by meekrohprocess 6y ago
Nice. The XTensa cores always felt weird.
Too bad they only included the I/M/C extensions - no floats, vectors, or atomics. And USB would be nice (nevermind, it has USB :D).
But it's still very exciting. Maybe there'll be less conflict between ARM/XTensa/PIC32/etc. cores in the coming years.
- baybal2 6y agoI believe the problem was XTensas not being available in hard macros, or at least Chen will not sell them at a price point a mortal can afford. That's a huge thing when power efficiency, and operation from battery mattered.
- Scaevolus 6y agoWhy do you need atomics on a single core device?
- praseodym 6y agoThere are ESP32 variants with a dual-core Xtensa processor (https://en.wikipedia.org/wiki/ESP32 https://en.wikipedia.org/wiki/ESP32).
- meekrohprocess 6y agoInterrupts and exceptions can happen at any point in a program's execution on a microcontroller, and they are free to modify memory and peripheral registers. >Load <register> >Modify register in memory >>Interrupt happens and changes <register> >Write incorrect value back to <register>. These sorts of bugs can be pernicious to debug, and they are easy for novice developers to create.
- yjftsjthsd-h 6y agoThat's horrifying. What is the fix/mitigation if you don't have proper atomics? I can't see how to properly avoid that.
- unwind 6y agoObviously interrupt code can't clobber registers like that, any shared register the ISR needs to share with ordinary code must be saved/restored on entry/exit somehow.
- loeg 6y agoI think GP is talking about MMIO or some device register rather than the CPU’s register file.
- loeg 6y agoYou implement higher-level abstractions like mutexes. On a single core device this could be as simple as masking interrupts. You can use the mutexes to avoid the described race.
- phkahler 6y agoOnly communicate in one direction. I write, you read. I can also provide a large coherent set of data so long as you dont read it until I mark it as ready. There are many other ways too.
- monocasa 6y agoYou just guard those sequences by disabling and reenabling interrupts around them. It's a very common pattern in systems not designed for SMP.
- meekrohprocess 6y agoYou can disable interrupts when modifying locking primitives, and save/restore the CPU context when interrupts are entered/exited. You can also minimize the amount of changes that any interrupt handler can make within the interrupt context. It's not really that bad, and plenty of microcontrollers lack atomic operations.
- chubs 6y agoIf you disable the interrupts, does that mean any incoming events get ignored, or simply queued for later? If the former, that sounds like you risk missing something important.
- stefan_ 6y agoBecause you are likely still running a preemptive multitasking operating system.
- azdle 6y ago> And USB would be nice. The block diagram show "USB Device" in the peripherals block.
- meekrohprocess 6y agoOh yeah, cool - I missed that. Finally! An Espressif chip with WiFi, Bluetooth, and USB!
- Sprite_tm 6y agoNote that the USB device is not a full-function software-controllable device; it provides a built-in 'serial port' and JTAG debugger only.
- sam_bristow 6y agoHaving a RISC-V based ESP also means it should be easy to add support in Renode [1]. [1]https://renode.io/ https://renode.io/