3 ms·
Yup, that's correct, the design is implemented in Wyre, which is a hardware definition language that I created. The language compiles to Verilog so it can work
by nickmqb 6y ago
Yup, that's correct, the design is implemented in Wyre, which is a hardware definition language that I created. The language compiles to Verilog so it can work with existing hardware development toolchains. The language is open source and can be found here: https://github.com/nickmqb/wyre https://github.com/nickmqb/wyre
- OJFord 6y agoI like the sound of that, but my verilog's rusty, a suggestion for the readme: show what the equivalent verilog would be for the example, or better I suppose the actual verilog that it would transpile to. I suppose your target audience is mainly more familiar with verilog (though not necessarily I suppose - could have only ever used VHDL) but I'm interested in playing with it, just haven't used verilog, or FPGAs at all, since university.
- ithkuil 6y agoTake a look at the examples dir on github: https://github.com/nickmqb/wyre/tree/master/examples https://github.com/nickmqb/wyre/tree/master/examples Then look at the "output" subdirectory and you'll find a verilog generated file for each example of the parent directory.