That's crazy. The entire 18 GB is directly adjacent to ALUs with no cache hierarchy? Also: "the on-wafer interconnect can send out one 32-bit pair of 16-bit wo

That's crazy. The entire 18 GB is directly adjacent to ALUs with no cache hierarchy? Also: "the on-wafer interconnect can send out one 32-bit pair of 16-bit words to each of a given core’s four neighbors on every machine cycle and can take in one 32-bit word on the same cycle. [...] supercomputers require a ratio of perhaps one word communicated per 1,000 floating point operations."