5 ms·
Closer to the core, better performance.
by jagged-chisel 6y ago
Closer to the core, better performance.
- PowerfulWizard 6y agoYeah, I'm looking at the rationale for HBM which looks physically similar and it seems to be closeness and the ability to have more wires. https://en.wikipedia.org/wiki/High_Bandwidth_Memory https://en.wikipedia.org/wiki/High_Bandwidth_Memory But the HBM photos have the 'interposer' layer and look to be using bare dies, the M1 looks to not have the interposer and to be using the DRAM package. I'm not fully convinced with why the DRAM needs to be on the M1 but there must be a reason. Apple's marketing site says their 'Unified Memeory Architecture' uses a 'custom package' so maybe the DRAM package appearance is the same but the interface is not.
- AnotherGoodName 6y agoI wonder if this will become the norm for all CPU manufacturers at some point. If they put 64Gb directly next to a high end CPU and that made it 10% faster all around i suspect it would be a pretty popular choice despite the lack of upgradability.
- stickyricky 6y agoI think for the most part upgrading RAM (capacity-wise) has been pretty stable (for my uses at least - programming and games). I've been on 16gb since...well as long as I can remember. Every time I upgrade I'm jumping from DDR2 to 3 to 4 and probably soon 5. So its not like I keep the sticks anyway. Even when I stay on DDR4 I have to upgrade because the speed of the RAM is too slow to feed the processor. Its unfortunately rare for me to not have to buy RAM with a new CPU.
- goatinaboat 6y agoIf they put 64Gb directly next to a high end CPU and that made it 10% faster all around i suspect it would be a pretty popular choice despite the lack of upgradability. What about ECC?
- wmf 6y agoAs usual, the uncrippled "workstation" version will have ECC and the crippled "consumer" version won't.
- goatinaboat 6y agoI mean, ECC is going to mean lower yields from the fab and a higher TDP. Will it be worth it?
- wmf 6y agoI don't see why that would be the case.
- goatinaboat 6y agoBecause it’s half the density of non-ECC so bigger wafers, and runs at a higher voltage?
- fomine3 6y agoDDR4 ECC needs just 1 parity chip for 8 chip, not half. Of course it consumes a bit more power to calculate checksum. IMO it worth for every computing.
- epistasis 6y agoThe RAM latency was still up at 90ns, as measured by Anandtech, so I'm not sure it's increasing performance much. Perhaps it's beneficial for reduced power consumption? Or maybe it's just a design holdover from mobile, and it was the easiest place to put the RAM. Though some people see upgradable RAM as a necessity, I'm not sure how often it actually happens in practice, if you look across consumers. I can't remember the last time I changed the RAM configuration after assembling a PC. One has to be a huge tinkerer for that to even enter into the picture.
- kube-system 6y agoIf most people are like me, they like socketed RAM because they can buy the cheaper low end model and immediately add RAM. But now that the whole industry is apparently going to non-socketed RAM, I don't think this is going to be much of a differentiator anymore. If there was an XPS or ThinkPad with a Ryzen and socketed RAM, I would have already bought it... but if the choice is between a $1400 non-socketed MacBook or a $1400 non-socketed ThinkPad... that's a tough choice.
- jaguar1878 6y agoPower consumption and package pinout/motherboard simplification would be the main two benefits. Latency in DRAM access is dominated by the controller logic on the CPU side (minority) and the bank access and amplification circuitry on the DRAM side (majority). Time of flight down the wires is fairly negligible. Power draw for the interface does scale meaningfully with wire length though. Also, routing the 100+ signals (command, address, data, reference voltages) can be a challenge, especially if the package is constrained on pin count. The tradeoff is that maximum RAM capacity is significantly reduced. Die can be thinned and stacked quite high, but the need to share command, address, data busses means signal integrity problems and increased power for the interface with no performance increase. Stacking die has yield issues as well, so cost rises faster than linear. And finally, power dissipation becomes a real issue, DRAM doesn't like getting too hot and the bottom of that stack is a long way from the heatsink.
- sliken 6y agoLikely makes it easier/cheaper to run DDR4X at 4500 Mhz. Also DDR4x is often dual channel and Anandtech claims the M1 has a 128 bit wide interface in the form of 8 16 bit channels. So ML, GPU, and CPU duty can have more load/stores in flight and might help explain why the M1 performs so well.