4 ms·

Something I was personally wondering about is how the DRAM was added to the M1 'chip'. This image shows clearly: http://web.archive.org/web/20201118042108/https

Something I was personally wondering about is how the DRAM was added to the M1 'chip'. This image shows clearly: http://web.archive.org/web/20201118042108/https://egpu.io/wp-content/uploads/2020/11/2020-m1-mac-mini-unboxing-processor-thunderbolt-4-controllers.jpg http://web.archive.org/web/20201118042108/https://egpu.io/wp... I guess they must be using much higher density for their 16G than a typical 16G SODIMM for example. I'm not fully understanding why the memory chips need to be on the M1 package if they're using the same package as all other memory.

jagged-chisel 6y ago
Closer to the core, better performance.
- PowerfulWizard 6y ago
  Yeah, I'm looking at the rationale for HBM which looks physically similar and it seems to be closeness and the ability to have more wires. https://en.wikipedia.org/wiki/High_Bandwidth_Memory https://en.wikipedia.org/wiki/High_Bandwidth_Memory But the HBM photos have the 'interposer' layer and look to be using bare dies, the M1 looks to not have the interposer and to be using the DRAM package. I'm not fully convinced with why the DRAM needs to be on the M1 but there must be a reason. Apple's marketing site says their 'Unified Memeory Architecture' uses a 'custom package' so maybe the DRAM package appearance is the same but the interface is not.
- AnotherGoodName 6y ago
  I wonder if this will become the norm for all CPU manufacturers at some point. If they put 64Gb directly next to a high end CPU and that made it 10% faster all around i suspect it would be a pretty popular choice despite the lack of upgradability.
  - stickyricky 6y ago
    I think for the most part upgrading RAM (capacity-wise) has been pretty stable (for my uses at least - programming and games). I've been on 16gb since...well as long as I can remember. Every time I upgrade I'm jumping from DDR2 to 3 to 4 and probably soon 5. So its not like I keep the sticks anyway. Even when I stay on DDR4 I have to upgrade because the speed of the RAM is too slow to feed the processor. Its unfortunately rare for me to not have to buy RAM with a new CPU.
  - goatinaboat 6y ago
    If they put 64Gb directly next to a high end CPU and that made it 10% faster all around i suspect it would be a pretty popular choice despite the lack of upgradability. What about ECC?
    - wmf 6y ago
      As usual, the uncrippled "workstation" version will have ECC and the crippled "consumer" version won't.
      - goatinaboat 6y ago
        I mean, ECC is going to mean lower yields from the fab and a higher TDP. Will it be worth it?
        wmf 6y ago
        I don't see why that would be the case.
        goatinaboat 6y ago
        Because it’s half the density of non-ECC so bigger wafers, and runs at a higher voltage?
        fomine3 6y ago
        DDR4 ECC needs just 1 parity chip for 8 chip, not half. Of course it consumes a bit more power to calculate checksum. IMO it worth for every computing.
- epistasis 6y ago
  The RAM latency was still up at 90ns, as measured by Anandtech, so I'm not sure it's increasing performance much. Perhaps it's beneficial for reduced power consumption? Or maybe it's just a design holdover from mobile, and it was the easiest place to put the RAM. Though some people see upgradable RAM as a necessity, I'm not sure how often it actually happens in practice, if you look across consumers. I can't remember the last time I changed the RAM configuration after assembling a PC. One has to be a huge tinkerer for that to even enter into the picture.
  - kube-system 6y ago
    If most people are like me, they like socketed RAM because they can buy the cheaper low end model and immediately add RAM. But now that the whole industry is apparently going to non-socketed RAM, I don't think this is going to be much of a differentiator anymore. If there was an XPS or ThinkPad with a Ryzen and socketed RAM, I would have already bought it... but if the choice is between a $1400 non-socketed MacBook or a $1400 non-socketed ThinkPad... that's a tough choice.
  - jaguar1878 6y ago
    Power consumption and package pinout/motherboard simplification would be the main two benefits. Latency in DRAM access is dominated by the controller logic on the CPU side (minority) and the bank access and amplification circuitry on the DRAM side (majority). Time of flight down the wires is fairly negligible. Power draw for the interface does scale meaningfully with wire length though. Also, routing the 100+ signals (command, address, data, reference voltages) can be a challenge, especially if the package is constrained on pin count. The tradeoff is that maximum RAM capacity is significantly reduced. Die can be thinned and stacked quite high, but the need to share command, address, data busses means signal integrity problems and increased power for the interface with no performance increase. Stacking die has yield issues as well, so cost rises faster than linear. And finally, power dissipation becomes a real issue, DRAM doesn't like getting too hot and the bottom of that stack is a long way from the heatsink.
  - sliken 6y ago
    Likely makes it easier/cheaper to run DDR4X at 4500 Mhz. Also DDR4x is often dual channel and Anandtech claims the M1 has a 128 bit wide interface in the form of 8 16 bit channels. So ML, GPU, and CPU duty can have more load/stores in flight and might help explain why the M1 performs so well.
smitty1110 6y ago
A big part of the reason is that the CPU, GPU, and neural engine all have direct access to the memory. That's the idea behind the unified memory that Apple talked about during the keynote. Compare this to a normal setup, where you have main memory and dedicated VRAM. You load something into a game by fetching it into RAM, and then loading it into VRAM by dispatching it over PCIe to the graphics card processor, which then stores it in VRAM. There's a lot of extra steps. My guess is that their memory subsystem is fairly radical to handle the different types of memory access for the different functional subsystems, so they optimized for specific memory modules. I really would love to see some more documentation on the M1 memory subsystem, there are so many unknowns behind the very impressive performance numbers we've seen over the past few days. And I personally suspect that the future will have traditional ram, with the on-chip ram acting as a kind of last level cache. You can't really scale this to 64GB or higher without some major thermal problems.
- deleted 6y ago
  [deleted]
- fulafel 6y ago
  The LPDDR4X memory chips in the M1 work about the same way as any modern iGPU or mobile SoC setup, the shared cpu/gpu memory controller arbitrates access to the DRAM.
- rodgerd 6y ago
  > . And I personally suspect that the future will have traditional ram, with the on-chip ram acting as a kind of last level cache. Amiga Chip RAM/Fast RAM is the new hotness.
walrus01 6y ago
> This image shows clearly: http://web.archive.org/web/20201118042108/https://egpu.io/wp http://web.archive.org/web/20201118042108/https://egpu.io/wp... It's like a much smaller, more advanced version of how the adjacent cache RAM was soldered onto the same circuit board on a Slot 1, Pentium 2 CPU. https://cdn11.bigcommerce.com/s-a1x7hg2jgk/images/stencil/1280x1280/products/10100/51178/intel-pentium-ii-350mhz-slot-1-cpu-sl37f-2.39__72522.1490004842.jpg?c=2?imbypass=on https://cdn11.bigcommerce.com/s-a1x7hg2jgk/images/stencil/12... The RAM is not actually part of the CPU die. It looks to me like the separate green PCB that contains both the CPU and the RAM has a ball grid array on its underside, and is then attached to the motherboard.
dboreham 6y ago
> I'm not fully understanding why the memory chips need to be on the M1 package if they're using the same package as all other memory Some guesses: Reduces the number of pins (lands these days) on the CPU package which in turn reduces cost and potentially improves thermal efficiency due to freeing up space previously used by pins to be used to conduct heat away from the die. Improved performance due to shortened traces between CPU and memory die. Ability to remove ESD protection circuitry from both CPU and memory pads, thus improving performance. Reduced power consumption due to lower inductance in CPU <-> memory traces because they're shorter. Arrangement anticipates a future SoC with DRAM on-die, without motherboard redesign. Somewhat more secure due to difficulty probing CPU <-> memory traces.
- jdsully 6y ago
  Each land/pin conducts heat so the more the better for thermal conduction. But these CPUs use so little power its not a big deal regardless.
  - naravara 6y ago
    > Each land/pin conducts heat so the more the better for thermal conduction. But these CPUs use so little power its not a big deal regardless. Is it possible this is part of a plan for a future high-performance Mac Pro SOC where power consumption ends up being much higher?

jagged-chisel 6y ago

Closer to the core, better performance.

PowerfulWizard 6y ago
Yeah, I'm looking at the rationale for HBM which looks physically similar and it seems to be closeness and the ability to have more wires. https://en.wikipedia.org/wiki/High_Bandwidth_Memory https://en.wikipedia.org/wiki/High_Bandwidth_Memory But the HBM photos have the 'interposer' layer and look to be using bare dies, the M1 looks to not have the interposer and to be using the DRAM package. I'm not fully convinced with why the DRAM needs to be on the M1 but there must be a reason. Apple's marketing site says their 'Unified Memeory Architecture' uses a 'custom package' so maybe the DRAM package appearance is the same but the interface is not.
AnotherGoodName 6y ago
I wonder if this will become the norm for all CPU manufacturers at some point. If they put 64Gb directly next to a high end CPU and that made it 10% faster all around i suspect it would be a pretty popular choice despite the lack of upgradability.
- stickyricky 6y ago
  I think for the most part upgrading RAM (capacity-wise) has been pretty stable (for my uses at least - programming and games). I've been on 16gb since...well as long as I can remember. Every time I upgrade I'm jumping from DDR2 to 3 to 4 and probably soon 5. So its not like I keep the sticks anyway. Even when I stay on DDR4 I have to upgrade because the speed of the RAM is too slow to feed the processor. Its unfortunately rare for me to not have to buy RAM with a new CPU.
- goatinaboat 6y ago
  If they put 64Gb directly next to a high end CPU and that made it 10% faster all around i suspect it would be a pretty popular choice despite the lack of upgradability. What about ECC?
  - wmf 6y ago
    As usual, the uncrippled "workstation" version will have ECC and the crippled "consumer" version won't.
    - goatinaboat 6y ago
      I mean, ECC is going to mean lower yields from the fab and a higher TDP. Will it be worth it?
      - wmf 6y ago
        I don't see why that would be the case.
        goatinaboat 6y ago
        Because it’s half the density of non-ECC so bigger wafers, and runs at a higher voltage?
        fomine3 6y ago
        DDR4 ECC needs just 1 parity chip for 8 chip, not half. Of course it consumes a bit more power to calculate checksum. IMO it worth for every computing.
epistasis 6y ago
The RAM latency was still up at 90ns, as measured by Anandtech, so I'm not sure it's increasing performance much. Perhaps it's beneficial for reduced power consumption? Or maybe it's just a design holdover from mobile, and it was the easiest place to put the RAM. Though some people see upgradable RAM as a necessity, I'm not sure how often it actually happens in practice, if you look across consumers. I can't remember the last time I changed the RAM configuration after assembling a PC. One has to be a huge tinkerer for that to even enter into the picture.
- kube-system 6y ago
  If most people are like me, they like socketed RAM because they can buy the cheaper low end model and immediately add RAM. But now that the whole industry is apparently going to non-socketed RAM, I don't think this is going to be much of a differentiator anymore. If there was an XPS or ThinkPad with a Ryzen and socketed RAM, I would have already bought it... but if the choice is between a $1400 non-socketed MacBook or a $1400 non-socketed ThinkPad... that's a tough choice.
- jaguar1878 6y ago
  Power consumption and package pinout/motherboard simplification would be the main two benefits. Latency in DRAM access is dominated by the controller logic on the CPU side (minority) and the bank access and amplification circuitry on the DRAM side (majority). Time of flight down the wires is fairly negligible. Power draw for the interface does scale meaningfully with wire length though. Also, routing the 100+ signals (command, address, data, reference voltages) can be a challenge, especially if the package is constrained on pin count. The tradeoff is that maximum RAM capacity is significantly reduced. Die can be thinned and stacked quite high, but the need to share command, address, data busses means signal integrity problems and increased power for the interface with no performance increase. Stacking die has yield issues as well, so cost rises faster than linear. And finally, power dissipation becomes a real issue, DRAM doesn't like getting too hot and the bottom of that stack is a long way from the heatsink.
- sliken 6y ago
  Likely makes it easier/cheaper to run DDR4X at 4500 Mhz. Also DDR4x is often dual channel and Anandtech claims the M1 has a 128 bit wide interface in the form of 8 16 bit channels. So ML, GPU, and CPU duty can have more load/stores in flight and might help explain why the M1 performs so well.

smitty1110 6y ago

A big part of the reason is that the CPU, GPU, and neural engine all have direct access to the memory. That's the idea behind the unified memory that Apple talked about during the keynote. Compare this to a normal setup, where you have main memory and dedicated VRAM. You load something into a game by fetching it into RAM, and then loading it into VRAM by dispatching it over PCIe to the graphics card processor, which then stores it in VRAM. There's a lot of extra steps. My guess is that their memory subsystem is fairly radical to handle the different types of memory access for the different functional subsystems, so they optimized for specific memory modules. I really would love to see some more documentation on the M1 memory subsystem, there are so many unknowns behind the very impressive performance numbers we've seen over the past few days. And I personally suspect that the future will have traditional ram, with the on-chip ram acting as a kind of last level cache. You can't really scale this to 64GB or higher without some major thermal problems.

deleted 6y ago
[deleted]
fulafel 6y ago
The LPDDR4X memory chips in the M1 work about the same way as any modern iGPU or mobile SoC setup, the shared cpu/gpu memory controller arbitrates access to the DRAM.
rodgerd 6y ago
> . And I personally suspect that the future will have traditional ram, with the on-chip ram acting as a kind of last level cache. Amiga Chip RAM/Fast RAM is the new hotness.

walrus01 6y ago

> This image shows clearly: http://web.archive.org/web/20201118042108/https://egpu.io/wp http://web.archive.org/web/20201118042108/https://egpu.io/wp... It's like a much smaller, more advanced version of how the adjacent cache RAM was soldered onto the same circuit board on a Slot 1, Pentium 2 CPU. https://cdn11.bigcommerce.com/s-a1x7hg2jgk/images/stencil/1280x1280/products/10100/51178/intel-pentium-ii-350mhz-slot-1-cpu-sl37f-2.39__72522.1490004842.jpg?c=2?imbypass=on https://cdn11.bigcommerce.com/s-a1x7hg2jgk/images/stencil/12... The RAM is not actually part of the CPU die. It looks to me like the separate green PCB that contains both the CPU and the RAM has a ball grid array on its underside, and is then attached to the motherboard.

dboreham 6y ago

> I'm not fully understanding why the memory chips need to be on the M1 package if they're using the same package as all other memory Some guesses: Reduces the number of pins (lands these days) on the CPU package which in turn reduces cost and potentially improves thermal efficiency due to freeing up space previously used by pins to be used to conduct heat away from the die. Improved performance due to shortened traces between CPU and memory die. Ability to remove ESD protection circuitry from both CPU and memory pads, thus improving performance. Reduced power consumption due to lower inductance in CPU <-> memory traces because they're shorter. Arrangement anticipates a future SoC with DRAM on-die, without motherboard redesign. Somewhat more secure due to difficulty probing CPU <-> memory traces.

jdsully 6y ago
Each land/pin conducts heat so the more the better for thermal conduction. But these CPUs use so little power its not a big deal regardless.
- naravara 6y ago
  > Each land/pin conducts heat so the more the better for thermal conduction. But these CPUs use so little power its not a big deal regardless. Is it possible this is part of a plan for a future high-performance Mac Pro SOC where power consumption ends up being much higher?