4 ms·
Does it? Apple's documentation seems to disagree [1]: "A weak memory ordering model, like the one in Apple silicon, gives the processor more flexibility to reo
by enzo1982 6y ago
Does it? Apple's documentation seems to disagree [1]:
"A weak memory ordering model, like the one in Apple silicon, gives the processor more flexibility to reorder memory instructions and improve performance, but doesn’t add implicit memory barriers."
[1] https://developer.apple.com/documentation/apple_silicon/addressing_architectural_differences_in_your_macos_code https://developer.apple.com/documentation/apple_silicon/addr...
- duskwuff 6y agoIt's switchable at runtime. Apple silicon can enable total store ordering on a per-thread basis while emulating x86_64, then turn it back off for maximum performance in native code. Here's a kernel extension someone built to manipulate this feature: https://github.com/saagarjha/TSOEnabler https://github.com/saagarjha/TSOEnabler