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Someone on that thread was saying that the M1 may be using on-chip DRAM as L2/L3 cache. Not sure how true that is.
by DarmokJalad1701 6y ago
Someone on that thread was saying that the M1 may be using on-chip DRAM as L2/L3 cache. Not sure how true that is.
- throwaheyy 6y agoDon’t most processors use on-chip SRAM for their cache, which is faster than DRAM?
- addaon 6y agoYes. The best-known exception is IBM's recent(-ish) power processors, which use large eDRAM as a last-level cache. As far as I know, there's no widespread use of eDRAM on processors smaller than 14 nm.
- dschuler 6y agoEvery layer in the storage hierarchy is "just a cache" in front the layer below it, so the naming is somewhat arbitrary. L1/L2/L3 caches are transparent from the perspective of the processor - it only sees a change in access times to main memory. Any advancement in the storage hierarchy means reducing latency at one level or increasing the amount of memory at that level. Most caches would use SRAM instead of DRAM, but the technology used doesn't define its role. Microcontrollers often have only embedded SRAM, serving as main memory.