3 ms·

What kind of design choices are they making that can get the power down so low? What's Intel doing that hasn't been optimized away after generations?

fooker 6y ago
Two things afaik: * Decoding an x86 instruction takes a ridiculous amount of resources. Can't be optimized away because of backwards compatibility. * Limited to small pages without jumping through weird OS hoops.
- PeCaN 6y ago
  - it takes some die space sure but no x86 processors are actually limited by instruction decoding (except, iirc, the first generation xeon phi in some cases) - huge pages don't exactly require weird OS hoops although i agree the 4kb→2mb→1gb page sizes are inconvenient
hmottestad 6y ago
I saw an interview with the designers of ARM and they explained how their design was ridiculously more efficient than competitors. Don’t have a link. Another good source of info is the article over at anandtech. Apple is doing a lot of stuff they Intel can’t because of x86. And also a bunch of stuff that neither Intel nor AMD want to do. Also don’t forget that Apple is on TSMC 5nm while Intel is for the most part on Intel 14nm which is more or less equivalent to TSMC 10nm.
- tehjoker 6y ago
  Thanks for the tip! I thought power consumption issues increase with decreasing size though due to leakage current though a change in the finFET design can help manage that.
  - heisenbit 6y ago
    Yes, so per area there will be more power consumption. But you need less area so if the transistor count stays the same you save.
95014_refugee 6y ago
Everything is very, very close together. LPDDR and very short trace lengths. Very few high-power PHYs. Lots of on-die cache. Conway's Law playing out, really.
tobyhinloopen 6y ago
Maybe it’s because Apple/ARM can ditch all legacy x86 stuff so the chips only contain instructions relevant for today, saving space for more transistors to do these relevant instructions or just to keep the chip smaller and more efficient
- hvidgaard 6y ago
  Underneath the x86/x64 ISA is a really different architecture. So to reach the backwards compatibility it needs a x86/x64 decoder and that is not a significant portion of the silicon as far as I know. Those instructions might be somewhat inefficient, but this is not really an issue when comparing, any ARM chip emulating will have to tackle the same problem. If Apples chip does not need this backwards compatibility, they essentially have to do it in software when emulating. They do this with a combination of recompilation at install time and some emulation at runtime. I suspect the compilation step is one of the main contributors to this boost in speed and efficiency. Windows could do the same, optimize the executable to better fit the underlying chip.

fooker 6y ago

Two things afaik: * Decoding an x86 instruction takes a ridiculous amount of resources. Can't be optimized away because of backwards compatibility. * Limited to small pages without jumping through weird OS hoops.

PeCaN 6y ago
- it takes some die space sure but no x86 processors are actually limited by instruction decoding (except, iirc, the first generation xeon phi in some cases) - huge pages don't exactly require weird OS hoops although i agree the 4kb→2mb→1gb page sizes are inconvenient

hmottestad 6y ago

I saw an interview with the designers of ARM and they explained how their design was ridiculously more efficient than competitors. Don’t have a link. Another good source of info is the article over at anandtech. Apple is doing a lot of stuff they Intel can’t because of x86. And also a bunch of stuff that neither Intel nor AMD want to do. Also don’t forget that Apple is on TSMC 5nm while Intel is for the most part on Intel 14nm which is more or less equivalent to TSMC 10nm.

tehjoker 6y ago
Thanks for the tip! I thought power consumption issues increase with decreasing size though due to leakage current though a change in the finFET design can help manage that.
- heisenbit 6y ago
  Yes, so per area there will be more power consumption. But you need less area so if the transistor count stays the same you save.

95014_refugee 6y ago

Everything is very, very close together. LPDDR and very short trace lengths. Very few high-power PHYs. Lots of on-die cache. Conway's Law playing out, really.

tobyhinloopen 6y ago

Maybe it’s because Apple/ARM can ditch all legacy x86 stuff so the chips only contain instructions relevant for today, saving space for more transistors to do these relevant instructions or just to keep the chip smaller and more efficient

hvidgaard 6y ago
Underneath the x86/x64 ISA is a really different architecture. So to reach the backwards compatibility it needs a x86/x64 decoder and that is not a significant portion of the silicon as far as I know. Those instructions might be somewhat inefficient, but this is not really an issue when comparing, any ARM chip emulating will have to tackle the same problem. If Apples chip does not need this backwards compatibility, they essentially have to do it in software when emulating. They do this with a combination of recompilation at install time and some emulation at runtime. I suspect the compilation step is one of the main contributors to this boost in speed and efficiency. Windows could do the same, optimize the executable to better fit the underlying chip.