3 ms·

Love the articles. I definitely want to spend a bit more time with it. The section on the sense amp was great. But one thing I was left wondering was how was

by egsmi 6y ago

Love the articles. I definitely want to spend a bit more time with it. The section on the sense amp was great. But one thing I was left wondering was how was the refresh managed? Was it just the act the reading/writing had the side effect of refreshing? Therefore the memory controller had to keep track of when & what was accessed?

PhantomGremlin 6y ago
Therefore the memory controller had to keep track of when & what was accessed? It was much more simple than that. A typical DRAM of the era had 128 rows (at least as externally visible; what's inside is up to the DRAM implementer). So in a higher end system the memory controller, about every 15 microseconds, would increment a 7-bit binary counter. It then would command all the DRAMs to simultaneously do a refresh cycle with this specific row address. This refresh took priority over normal read and write. No need to optimize refresh by skipping it for rows which had recently been accessed. Just blindly refresh all 128 rows in sequence. Internally a 16k bit DRAM would have 128 rows and 128 columns. Each time a row is read, all 128 associated columns are read in parallel. Then the contents of the selected single column are output. That's what makes refresh work without consuming too much of the chips bandwidth. A refresh of a row results in all 128 columns of that row being refreshed. It takes about 2000 microseconds to do 128 refreshes. That's often what the DRAM chip was specified for. In reality the chips could often retain content for a minute at room temperature. It was when operating at the limit of 70C that refresh every 2 milliseconds became close to necessary. Some microprocessors of the era, such as the Z80, had an internal 7 bit counter. The Z80 could be easily set up to send this 7-bit counter out to the DRAM after every instruction fetch. So a Z80 system did something like this: fetch an 8-bit opcode refresh the next 1 of 128 rows of DRAM fetch additional instruction bytes complete the instruction Since a Z80 operated at about 2 MHz minimum and instructions completed in about 6 cycles, DRAM memory was being refeshed, once per instruction, at a much faster rate than the chips needed. There was no such thing as slow divide instructions. The worst case IIRC was about 12 or so cycles to complete an instruction. The only downside to this sort of refresh is in systems that have more than one word width's worth of chips. A normal read or write accessed a single word. Simple refresh accessed all DRAM chips in parallel. Much higher power consumption. So, e.g. 16 K bytes of memory needed 8 DRAM chips. Whereas 64 K bytes of memory needed 32 DRAM chips. In a Z80 system, which read 8 bits at a time, only 8 chips would be active during normal read/write but all 32 chips would be active in refresh. A DRAM chip that was idle consumed a few mW of power whereas a DRAM chip that was being accessed or refreshed consumed a few hundred mW of power. So in a large system (hundreds of chips) you couldn't take as simplistic an approach to refresh as the Z80 did.
- egsmi 6y ago
  Thanks for that! It’s very clear now.

by egsmi 6y ago

PhantomGremlin 6y ago

Therefore the memory controller had to keep track of when & what was accessed? It was much more simple than that. A typical DRAM of the era had 128 rows (at least as externally visible; what's inside is up to the DRAM implementer). So in a higher end system the memory controller, about every 15 microseconds, would increment a 7-bit binary counter. It then would command all the DRAMs to simultaneously do a refresh cycle with this specific row address. This refresh took priority over normal read and write. No need to optimize refresh by skipping it for rows which had recently been accessed. Just blindly refresh all 128 rows in sequence. Internally a 16k bit DRAM would have 128 rows and 128 columns. Each time a row is read, all 128 associated columns are read in parallel. Then the contents of the selected single column are output. That's what makes refresh work without consuming too much of the chips bandwidth. A refresh of a row results in all 128 columns of that row being refreshed. It takes about 2000 microseconds to do 128 refreshes. That's often what the DRAM chip was specified for. In reality the chips could often retain content for a minute at room temperature. It was when operating at the limit of 70C that refresh every 2 milliseconds became close to necessary. Some microprocessors of the era, such as the Z80, had an internal 7 bit counter. The Z80 could be easily set up to send this 7-bit counter out to the DRAM after every instruction fetch. So a Z80 system did something like this: fetch an 8-bit opcode refresh the next 1 of 128 rows of DRAM fetch additional instruction bytes complete the instruction Since a Z80 operated at about 2 MHz minimum and instructions completed in about 6 cycles, DRAM memory was being refeshed, once per instruction, at a much faster rate than the chips needed. There was no such thing as slow divide instructions. The worst case IIRC was about 12 or so cycles to complete an instruction. The only downside to this sort of refresh is in systems that have more than one word width's worth of chips. A normal read or write accessed a single word. Simple refresh accessed all DRAM chips in parallel. Much higher power consumption. So, e.g. 16 K bytes of memory needed 8 DRAM chips. Whereas 64 K bytes of memory needed 32 DRAM chips. In a Z80 system, which read 8 bits at a time, only 8 chips would be active during normal read/write but all 32 chips would be active in refresh. A DRAM chip that was idle consumed a few mW of power whereas a DRAM chip that was being accessed or refreshed consumed a few hundred mW of power. So in a large system (hundreds of chips) you couldn't take as simplistic an approach to refresh as the Z80 did.

egsmi 6y ago
Thanks for that! It’s very clear now.