5 ms·
Apple’s core is very wide. But wide usually means very high power consumption. M1 apparently has much lower power consumption. So something else is going on
by frogblast 6y ago
Apple’s core is very wide. But wide usually means very high power consumption.
M1 apparently has much lower power consumption.
So something else is going on other than “Apple is willing to spend more to make cores wider”.
- BlueTemplar 6y ago> M1 apparently has much lower power consumption. Even compared to similar manufacturing processes ?
- Miraste 6y agoThere are no similar manufacturing processes, Apple has paid for time-limited exclusivity on 5nm.
- tuatoru 6y agoThe manufacturing process is TSMC's, so probably not. To me the innovation is using phone-type SoC technology. A lot of the power (and die area) demand in modern chips is in the interface circuitry to drive the few centimetres of PCB trace between ICs. Put the RAM in the same package as the CPU and you eliminate that interface. That gives you die space and power budget for big buffers and lots of parallel execution. Interface transistors (and wires) are many times larger than the core compute logic transistors (and wires), so there is much more than a one-for-one gain.
- DeRock 6y agoThat, in part, comes from x86 vs arm. x86, with its variable length instructions, means your logic gets increasingly complex as you widen. Meanwhile with arm, you have constant instruction size (other than thumb, but that’s more straightforward than variable size), that lets Apple do things like an 8-bit wide decode block (vs. 4-bit for Intel) and a humongous 630 OOB (almost double Intel’s deepest cores).
- sidewndr46 6y agoFor the uneducated, what is an "OOB" here?
- sounds 6y agoI think that's a typo - the Apple Silicon M1 has a "ROB is in the 630 instruction range" - https://www.anandtech.com/show/16226/apple-silicon-m1-a14-deep-dive/2 https://www.anandtech.com/show/16226/apple-silicon-m1-a14-de... "ROB" and "OOO" might have gotten mixed together here. OOO = Out-of-order. Refers to the fact that the M1 can decode instructions in parallel. ROB = Re-Order Buffer. Refers to the stage where the parallel instructions get put back "in-order" and "retired."
- deleted 6y ago[deleted]
- deleted 6y ago[deleted]
- jmull 6y agoFrom the Anandtech article[1] on the M1, I think this is referring to the reorder buffer, or ROB. Reorder buffers allow instructions to execute out-of-order, so maybe that's where the "OO" comes from. [1] https://www.anandtech.com/show/16226/apple-silicon-m1-a14-deep-dive https://www.anandtech.com/show/16226/apple-silicon-m1-a14-de...
- DeRock 6y agoYes, I was going by memory, which thought “out of order buffer” was a thing. I meant ROB. Point still stands, in that scaling these blocks is very difficult with variable instruction size.
- sounds 6y agoAnandTech's analysis corroborates what DeRock is saying here about the x86 variable length instructions being the limiting factor on how wide the decode stage can be. The other factor is Apple is using a "better" process node (TSMC 5nm). I put it in quotes because Intel's 10nm and upcoming nodes may be competitive, but Intel's 14nm is what Apple gets to compete against today, right now. Intel has been defeated in detail.
- andor 6y agoNot a chip designer, but I think it could lead to a more efficient use of the functional units. With more instructions decoded per clock and a larger reorder buffer, the core should be able to keep its units busier, i.e. not wasting energy without producing valuable output. This efficiency gain of course needs to outweigh the consumption of the additional decoders. This part is easier with ARM as decoding x86 is complicated. In addition to higher unit utilization, the increased parallelism should also be an advantage in the "race to sleep" power management strategy.