There's nothing to "reverse engineer" there: M1 has 4x the L1 cache and a wider bus. That's it. This cannot be implemented in AMD's current 7nm process due to

There's nothing to "reverse engineer" there: M1 has 4x the L1 cache and a wider bus. That's it. This cannot be implemented in AMD's current 7nm process due to size restrictions. The SoC-side of the story is also contrary to the very core design of a general purpose CPU. RAM, GPU, and extension cards for specialised tasks are already covered by 3rd party products on the PCIe and USB4 buses and AMD has no interest in cannibalising their GPU and console business... With their upcoming discrete GPUs and accelerator cards, Intel might be in the same boat w.r.t. SoC design.