What about the metrology cutouts you have to leave in every 2mm by 2mm region on 28nm and lower processes? I hear the interval is even smaller on 14nm/7nm. I

What about the metrology cutouts you have to leave in every 2mm by 2mm region on 28nm and lower processes? I hear the interval is even smaller on 14nm/7nm. I always thought those were only half for process control and half to force you to leave a blank spot on your mask where they could pattern in nasty additional circuitry on a few wafers. Edit: TSMC calls this the "Dummy TCD macro". If you have the 28nm design rule book T-N28-CL-DR-002 version 1.3 it's Section 6.3.3 "Dummy TCD Design Insertion Guideline" (if you don't have the design rule book then no, I can't send it to you, please don't ask). The TCD macro is a black box -- nobody outside TSMC gets to see what's in it. You have to leave a 9um*3.5um empty region on all layers in every 2mm by 2mm region of your maskset. Now that Multi Layer Maskset (MLM) is widespread every fab has the ability to "blade off" regions of a mask and expose a pattern from a different mask in that region (of course wafers processed this way are much much more expensive). The TCD macro rules force you to leave an empty hole in your design at regular intervals where this can be done without breaking your chip.