This is a risc chip, it's unlikely there's any microcode at all - I know of no RISC-V chip that has microcode. What there will be is a 0-stage boot ROM -it's n

This is a risc chip, it's unlikely there's any microcode at all - I know of no RISC-V chip that has microcode. What there will be is a 0-stage boot ROM -it's not microcode, just RISC-V code -essentially the code that knows how to get from the first instruction after reset up to and including the loading of u-boot (or whatever) - if you're interested in how open a system is ask to see that code, and all the code that runs in m-mode (probably u-boot-spl and opensbi both of which are open source)