> doesn't greater transistor density support more sophisticated architectures and hence superior IPC? Intel claims Rocket Lake will deliver 10% IPC improvement

> doesn't greater transistor density support more sophisticated architectures and hence superior IPC? Intel claims Rocket Lake will deliver 10% IPC improvement over Cannon Lake on the same 14nm node. Clearly 14nm hasn't been tapped out despite the five years and 3-4 (depending on who you ask) previous microarchitectures they've used it for. Yes, smaller devices enable better designs. Ironically if Rocket Lake actually delivers 10% then it's corroboration that Intel has been slacking on microarchitecture as well. > for the architecture team who have to design for two processes at the same time rather than focus on just 10nm? Intel has been designing devices for at least two nodes as SOP for 13 years now; they called it "tick-tock" which is the cycle of developing a new microarchitecture on one node and then porting to a smaller node. The difference this time is that they're going backwards... In any case the argument that there is some great difficulty with moving cores between nodes is tough to support given the history.