3 ms·
Can you really do an enormous SRAM on a bigger node without it occupying a huge surface? Would 14nm be cheap enough for that to be interesting? If so, why not a
by temac 6y ago
Can you really do an enormous SRAM on a bigger node without it occupying a huge surface? Would 14nm be cheap enough for that to be interesting? If so, why not also use it for other big structures?
- rbanffy 6y agoIBM does that on mainframes with DRAM as L4. A cluster of four sockets has almost a gigabyte of memory in a separate chip with analogous function as AMD's IO die (and that attaches to the memory modules). Of course, these are enormous and ridiculously expensive dies.
- bcrl 6y agoBut eDRAM uses less power than SRAM. A large SRAM on an older process would have a substantial power penalty.
- rbanffy 6y agoA completely different price-point and TDP, but the Xeon Phi had up to 16GB (out of the main die) that could act as a cache to main memory or mapped to a physical address range. No space for this on this package size, but EPYC package could fit it.
- labawi 6y agoI was pretty sure SRAM uses less power than DRAM. Some research shows it is true for 6T cells, but questionable on smaller 4T cells, depending on implementation. So, if you can use ~6x the area of eDRAM, you can have almost no power draw SRAM.