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Western Digital SweRV RISC-V Core
- chubs 6y agoSome information I found at https://codasip.com/swerv https://codasip.com/swerv: The SweRV Core™ EH1 is an advanced high-performance core with small footprint, suitable for embedded devices supporting data-intensive applications such as storage controllers, industrial IoT, real-time analytics in surveillance systems, and other smart systems. SweRV Core EH1: Architecture: 32-bit, dual superscalar, 9-stage pipeline Performance: Up to 4.95 CoreMark/MHz (further gain possible with compiler optimizations) Clock speed: Up to 1.8 GHz Technology: TSMC 28nm CMOS Bus support: AXI, AHB-lite Programmable Interrupt Controller RISC-V debug support
- jlokier 6y ago> Bus support: AXI, AHB-lite That's interesting. AXI is from ARM and I think it's still subject to ARM licensing.
- johntb86 6y agoI was surprised by that as well, but here's the term in the AXI license: "(i) where a product created under Clause 1(i) is an integrated circuit which includes a CPU then either: (a) such CPU shall only be manufactured under licence from ARM; or (b) such CPU is neither substantially compliant with nor marketed as being compliant with the ARM instruction sets licensed by ARM from time to time;" So it seems like they might be in the clear.
- unixhero 6y ago>Clock speed: Up to 1.8 GHz So clearly this must be possible to run DooM on.
- tyingq 6y agoPerhaps. No on-die floating point, though.
- mrbungie 6y agoDoom uses fixed-point arithmetic[1], so no problem. [1] https://doomwiki.org/wiki/Fixed_point https://doomwiki.org/wiki/Fixed_point
- leoc 6y agoAt the time of Doom's release many or most DOS/Windows PCs still didn't have hardware FPUs https://www.xtof.info/blog/?p=931 https://www.xtof.info/blog/?p=931 I think that using hardware floating-point would have prevented some of the early console releases too (particularly the SNES?)
- wk_end 6y agoThe SNES version was coded from scratch in 65816/Super FX assembly language [1]; how the PC version did things would’ve been neither here nor there. [1] https://github.com/RandalLinden/DOOM-FX https://github.com/RandalLinden/DOOM-FX - yes, that’s the original code on GitHub, released by the author
- MaxBarraclough 6y agoHN discussion on the release, 3 months ago: https://news.ycombinator.com/item?id=23989638 https://news.ycombinator.com/item?id=23989638
- Narishma 6y agoDoom doesn't use floating point.
- homarp 6y agosome more background: https://www.linkedin.com/pulse/2019-year-risc-v-open-source-silicon-olof-kindgren https://www.linkedin.com/pulse/2019-year-risc-v-open-source-...
- vxNsr 6y agoAs cool as this, WD should be blocklisted just because of their unfriendly practices around product naming and flouting conventions.
- reitzensteinm 6y agoIt pissed me off too, but if that's the threshold for a blacklist it's hard to think of a tech company that would make the cut.
- neolog 6y agoWhat does this refer to?
- meragrin_ 6y agoThey were selling NAS drives using shingled magnetic recording(SMR) without providing any hint the drives were SMR. There are a number of NAS setups which SMR drives cannot be used in.
- andoriyu 6y agoAlso, not showing real rotation speeds and calling what they show "5400 class" which wasn't 5400 at all.
- squarefoot 6y agoFrom what I know, plain WD Red drives are the only SMR drives produced by WD, and are the newest development; they just switched the names so that the old plain CMR WD Red disks became WD Red Plus. Therefore WD Red Plus and the faster WD Red Pro models should be 100% safe, while plain WD Red ones, especially if bought less than a couple years ago are not. Corrections welcome of course.
- sigjuice 6y agoTheir rebranding and name switching is not very reassuring to me. I ordered two Red Plus drives (WD101EFAX) last month, but the drives I got are labeled "Red". I remember seeing some fine print (maybe on their website or in the box I got) which said "you might get drives that look like they are Red, but we promise they totally are Red Plus ...". That said, the drives are working fine AFAICT and I honestly don't know enough about hard drives to tell the difference.
- G4E 6y agoDoes anyone know in which product they put this chip ? It would be fun to get it out and repurpose it on a custom board !
- duskwuff 6y agoIt's probably going to be deeply embedded in their hard disk controllers. Nothing you'd be able to easily reuse.
- userbinator 6y agoPeople still try... and achieve: https://spritesmods.com/?art=hddhack https://spritesmods.com/?art=hddhack
- ComputerGuru 6y agoSuch a humbling read. Thank you for sharing, I somehow did not come across this when it was previously making the rounds.
- dylan604 6y agoI've heard tales of persistent hacks from nation state type attackers by putting the malicious code onto certain chips like the various ROMs have, but this is the first time I've read this level of detail about someone's attempt that was not funded by a nation state. However, can these be delivered remotely without physical access to the hardware? My threat model is not one where I'm concerned about a physical attack, but because of INTERNET, I am curious about software only hack possibilities.
- brokenmachine 6y agoFrom page 6 of that (awesome!) article: After some messing around and guessing VSC parameters, fwtool could all of a sudden also read and write the flash of a HD attached to the PC it's run on. So a remote attacker who already had root access to run fwtool could do it.
- 6y ago
- pkaye 6y agoWould this fit on an FPGA?
- tverbeure 6y agoIt does, but it's not a great solution: https://tomverbeure.github.io/2019/03/13/SweRV.html#swerv-for-hobby-use https://tomverbeure.github.io/2019/03/13/SweRV.html#swerv-fo....
- sanxiyn 6y agoNote that this is EH1 version. EH2 is an update of EH1 and an improvement in all aspects. https://github.com/chipsalliance/Cores-SweRV-EH2 https://github.com/chipsalliance/Cores-SweRV-EH2
- wmf 6y agoIs it? It looked to me like EH2 might have lower single-thread performance.
- ohazi 6y agoIf you're looking to start playing around with a RISC-V that fits on a small FPGA, PicoRV32 [1] is a good option. It's written/maintained by Claire Wolf, who also started the yosys and icestorm open source synthesis projects. PicoRV32 is particularly neat because it includes an SoC wrapper [2] that allows you to place other hardware / co-processors / peripherals on the same FPGA and talk to them from the CPU via a memory mapped interface. [1] https://github.com/cliffordwolf/picorv32 https://github.com/cliffordwolf/picorv32 [2] https://github.com/cliffordwolf/picorv32/tree/master/picosoc https://github.com/cliffordwolf/picorv32/tree/master/picosoc
- mleonhard 6y agoLots of documentation: https://github.com/Codasip/SweRV-Support-Package-free https://github.com/Codasip/SweRV-Support-Package-free
- hajile 6y agoI wonder how much money they've saved using RISC-V. ARM used to license (2013) for 1-10 million up front then 1-2% of the street value of the chip in royalties[0]. A little googling find this presentation on swerve [1] EH2 which says 4.9 coremark/mhz with one core. It's 8 stage, dual core (with SMT) targeting 1.2GHz on 16nm. It seems likely to be between an a35 (wearable) and a55. With those chips starting at around $10 and around 100m units per year, it's easily 11-30 million per year but including the fact that integrating the arm core is also expensive and requires engineers. That money represents 22-60 full time engineers at $500,000 each. They also have a m4 sized chip too which is another big chunk of money These big companies stand to save a lot moving to RISC-V. [0] https://www.neowin.net/news/arm-reportedly-hiking-licensing-fees-of-its-chips-by-four-times-for-some-customers/ https://www.neowin.net/news/arm-reportedly-hiking-licensing-... [1] https://riscv.org/wp-content/uploads/2019/12/12.11-14.20a3-Bandic-WD_SweRV_Cores_Roadmap_v4SCR.pdf https://riscv.org/wp-content/uploads/2019/12/12.11-14.20a3-B...
- nickik 6y agoGiven the amount of investment WD has made into the ecosystem its questionable how much money they have made yet. In the long run they will make a fair amount of money, but the cost of developing all these chips, supporting the open source ecosystem and tooling and so on is not free. Apparently they were able to take over the SPARC people that were dropped by Oracle.
- dogma1138 6y agoRISC-V doesn’t come with the patents needed to build a modern high performance CPU. Building modern CPUs isn’t about the ISA of Intel made the x86 ISA open to all tomorrow you still would need a plethora of patents licensed to ship a CPU without being sued to oblivion.
- audunw 6y agoDo you have any examples of the kind of patents you would need to license? I don't anything in the ISA itself is covered by patents anymore. And the basic techniques for making a high performance CPU are getting quite old. Seems like a lot of the techniques used by desktop CPUs being released today have a a lot to do with advanced cache architectures, "AI" branch prediction, virtual memory, hypervisors, etc. A lot of these things will not be so relevant to a special purpose embedded CPU like this.
- ksec 6y agoOr similar from OpenPOWER, I thought people might be interested. https://github.com/antonblanchard/microwatt https://github.com/antonblanchard/microwatt