There's some odd stuff: <<< PDEP/PEXT Parallel Bits Deposit/Extreact 300 cycle latency 250 per clock 3 cycle latency 1 per clock It’s worth highlighting t

There's some odd stuff: <<< PDEP/PEXT Parallel Bits Deposit/Extreact 300 cycle latency 250 per clock 3 cycle latency 1 per clock It’s worth highlighting those last two commands. Software that helps the prefetchers, due to how AMD has arranged the branch predictors, can now process three prefetch commands per cycle. The other element is the introduction of a hardware accelerator with parallel bits: latency is reduced 99% and throughput is up 250x. >>> It talks about pdep/pext and links them to prefetchers - what? Weirder yet "is the introduction of a hardware accelerator with parallel bits" all that's happened, and backed up by earlier info in the article, is that these were trapped+emulated before, hence their hideous cost, and now they're in hardware[0]. It comes across as if someone didn't understand that. [0] calling it a 'hardware accelerator' is just peculiar.