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Zen4 might bring on-chiplet SRAM cache using a cheaper node
by sroussey 6y ago
Zen4 might bring on-chiplet SRAM cache using a cheaper node
- andy_ppp 6y agoIs that just a rumour or are ITK?
- wmf 6y agoI'm not sure what you're trying to say here. Zen2/3 already have 32MB L3 SRAM on each chiplet. And we know TSMC 5nm is more expensive than 7nm.
- sroussey 6y agoI mean on the IO die, not the processor one (or maybe a new one). 256MB L4 Infinity Cache for all the CPUs in the package. It doesn’t need to be on 5nm or 7nm. It can be on 14nm. But still on package. (I should have said on package, not on-chiplet, too late to edit)
- temac 6y agoCan you really do an enormous SRAM on a bigger node without it occupying a huge surface? Would 14nm be cheap enough for that to be interesting? If so, why not also use it for other big structures?
- rbanffy 6y agoIBM does that on mainframes with DRAM as L4. A cluster of four sockets has almost a gigabyte of memory in a separate chip with analogous function as AMD's IO die (and that attaches to the memory modules). Of course, these are enormous and ridiculously expensive dies.
- bcrl 6y agoBut eDRAM uses less power than SRAM. A large SRAM on an older process would have a substantial power penalty.
- rbanffy 6y agoA completely different price-point and TDP, but the Xeon Phi had up to 16GB (out of the main die) that could act as a cache to main memory or mapped to a physical address range. No space for this on this package size, but EPYC package could fit it.
- labawi 6y agoI was pretty sure SRAM uses less power than DRAM. Some research shows it is true for 6T cells, but questionable on smaller 4T cells, depending on implementation. So, if you can use ~6x the area of eDRAM, you can have almost no power draw SRAM.