4 ms·
> Data may only be kept (passed) in BEAM registers between instructions. > This may seem silly, aren’t machine registers faster? > Yes, but in practice not by
by haberman 6y ago
> Data may only be kept (passed) in BEAM registers between instructions.
> This may seem silly, aren’t machine registers faster?
> Yes, but in practice not by much and it would make things more complicated.
My understanding is that the latency of an L1 cache load is 5 cycles on recent Intel processors.
In tight code that is a really substantial overhead. I get that register allocation is complicated, and I totally see the benefit of simplicity, but it's hard not to think that this will significantly limit performance.
- didibus 6y agoIt does limit performance, but not in a relevant way for the type of applications Beam is designed for.
- CJefferson 6y agoOften, if your function is that small, inlining it is a better idea anyway?
- mathw 6y agoDon't lose sight of two things: Erlang is designed for massive, distributed, highly reliable network systems. Therefore, it is likely that a lot of Erlang code does a lot of waiting around for the network rather than needing every available CPU cycle. This is the first time they're releasing a JIT. They'll deliver their performance gains, and if they want to and it seems feasible they can come back and do further work in the future. But you have to put work in where it's valuable, and somehow I doubt RabbitMQ (for example) is going to care about this being missed this time around.
- a1369209993 6y agoIf the address of the BEAM register file (rbx, apparently) stays constant, and the last write to that register was >5 cycles ago, the load can be speculated 5 cycles in advance; if the last write was <5 cycles ago, my understanding is that that gets handled by store-to-load forwarding with a latency of ~0.
- CalChris 6y agoSkylake Client is "4 cycles for fastest load-to-use (simple pointer accesses) 5 cycles for complex addresses" https://en.wikichip.org/wiki/intel/microarchitectures/skylake_(client) https://en.wikichip.org/wiki/intel/microarchitectures/skylak...